[Mesa-dev] [PATCH v2 2/2] isl: the display engine requires 64B alignment for linear surfaces

[Lionel Landwerlin]

On 21/02/2019 13:30, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-02-21 12:57:09)
>> I did not find the PRM bit that says it must be 64b aligned, but I can
>> see that's what i915 checks.
>>
>> Chris: If you have a pointer to it, I could add the quote.
> In amongst the register specs,
> PLANE_STRIDE:
> For Linear memory, this field specifies the stride in chunks of 64 bytes (1 cache line).
> -Chris
>
Thanks a lot!