[Mesa-dev] [PATCH v2 2/2] isl: the display engine requires 64B alignment for linear surfaces

Chris Wilson chris at chris-wilson.co.uk
Thu Feb 21 13:30:24 UTC 2019

Quoting Lionel Landwerlin (2019-02-21 12:57:09)
> I did not find the PRM bit that says it must be 64b aligned, but I can 
> see that's what i915 checks.
> Chris: If you have a pointer to it, I could add the quote.

In amongst the register specs,
For Linear memory, this field specifies the stride in chunks of 64 bytes (1 cache line).

More information about the mesa-dev mailing list