[Mesa-dev] [PATCH v3 19/42] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits

[Jason Ekstrand]

On Tue, Jan 15, 2019 at 7:55 AM Iago Toral Quiroga <itoral at igalia.com>
wrote:

> We are now using these bits, so don't assert that they are not set, just
> avoid compaction in that case.
>
> Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
> ---
>  src/intel/compiler/brw_eu_compact.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_eu_compact.c
> b/src/intel/compiler/brw_eu_compact.c
> index ae14ef10ec0..20fed254331 100644
> --- a/src/intel/compiler/brw_eu_compact.c
> +++ b/src/intel/compiler/brw_eu_compact.c
> @@ -928,8 +928,11 @@ has_3src_unmapped_bits(const struct gen_device_info
> *devinfo,
>        assert(!brw_inst_bits(src, 127, 126) &&
>               !brw_inst_bits(src, 105, 105) &&
>               !brw_inst_bits(src, 84, 84) &&
> -             !brw_inst_bits(src, 36, 35) &&
>               !brw_inst_bits(src, 7,  7));
> +
> +      /* Src1Type and Src2Type, used for mixed-precision floating point */
> +      if (brw_inst_bits(src, 36, 35))
> +         return true;
>

You're only doing this in the broadwell case.  What about SKL+ and CHV?
Can we compact mixed-precision stuff there?  Looks like maybe we can but
there should be at least something in the commit message about that.


>     }
>
>     return false;
> --
> 2.17.1
>
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