[Mesa-dev] [PATCH v2] gm107/ir: Add stg, ldg instructions and function for checking offset length
Mark Menzynski
mmenzyns at redhat.com
Tue Jul 23 13:35:38 UTC 2019
Nvidia actively uses these instructions, maybe they are better in
something.
Long offset checking function was made because these functions only have 24 bit
address offsets.
v2: removed long offset funnction
Signed-off-by: Mark Menzynski <mmenzyns at redhat.com>
---
.../nouveau/codegen/nv50_ir_emit_gm107.cpp | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 6eefe8f0025..8da5adb94ce 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -174,9 +174,11 @@ private:
void emitLDC();
void emitLDL();
void emitLDS();
+ void emitLDG();
void emitLD();
void emitSTL();
void emitSTS();
+ void emitSTG();
void emitST();
void emitALD();
void emitAST();
@@ -2414,6 +2416,17 @@ CodeEmitterGM107::emitLDS()
emitGPR (0x00, insn->def(0));
}
+void
+CodeEmitterGM107::emitLDG()
+{
+ emitInsn (0xeed00000);
+ emitLDSTs(0x30, insn->dType);
+ emitLDSTc(0x2e);
+ emitField(0x2d, 1, insn->src(0).getIndirect(0)->getSize() == 8);
+ emitADDR (0x08, 0x14, 24, 0, insn->src(0));
+ emitGPR (0x00, insn->def(0));
+}
+
void
CodeEmitterGM107::emitLD()
{
@@ -2445,6 +2458,17 @@ CodeEmitterGM107::emitSTS()
emitGPR (0x00, insn->src(1));
}
+void
+CodeEmitterGM107::emitSTG()
+{
+ emitInsn (0xeed80000);
+ emitLDSTs(0x30, insn->dType);
+ emitLDSTc(0x2e);
+ emitField(0x2d, 1, insn->src(0).getIndirect(0)->getSize() == 8);
+ emitADDR (0x08, 0x14, 24, 0, insn->src(0));
+ emitGPR (0x00, insn->src(1));
+}
+
void
CodeEmitterGM107::emitST()
{
--
2.21.0
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