[Mesa-dev] [PATCH] ac: add radeon_info::is_amdgpu instead of checking drm_major == 3
Samuel Pitoiset
samuel.pitoiset at gmail.com
Thu Jun 13 07:01:13 UTC 2019
Why do you need that?
On 6/12/19 11:31 PM, Marek Olšák wrote:
> From: Marek Olšák <marek.olsak at amd.com>
>
> and clean up
> ---
> src/amd/common/ac_gpu_info.c | 13 ++++--
> src/amd/common/ac_gpu_info.h | 1 +
> src/amd/vulkan/radv_debug.c | 5 +-
> src/gallium/drivers/r600/r600_buffer_common.c | 6 +--
> src/gallium/drivers/r600/r600_pipe.c | 2 +-
> src/gallium/drivers/r600/r600_pipe_common.c | 46 ++-----------------
> src/gallium/drivers/r600/r600_query.c | 2 +-
> src/gallium/drivers/r600/r600_texture.c | 2 +-
> src/gallium/drivers/r600/radeon_uvd.c | 3 +-
> src/gallium/drivers/r600/radeon_vce.c | 5 +-
> src/gallium/drivers/radeon/radeon_uvd.c | 2 +-
> src/gallium/drivers/radeon/radeon_vce.c | 6 +--
> src/gallium/drivers/radeonsi/si_buffer.c | 2 +-
> src/gallium/drivers/radeonsi/si_debug.c | 2 +-
> src/gallium/drivers/radeonsi/si_get.c | 4 +-
> src/gallium/drivers/radeonsi/si_pipe.c | 4 +-
> src/gallium/drivers/radeonsi/si_query.c | 2 +-
> src/gallium/drivers/radeonsi/si_state.c | 2 +-
> .../winsys/radeon/drm/radeon_drm_winsys.c | 1 +
> 19 files changed, 33 insertions(+), 77 deletions(-)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index 13fba8df047..4de6882f15e 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -110,20 +110,23 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> if (r) {
> fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
> return false;
> }
> info->pci_domain = devinfo->businfo.pci->domain;
> info->pci_bus = devinfo->businfo.pci->bus;
> info->pci_dev = devinfo->businfo.pci->dev;
> info->pci_func = devinfo->businfo.pci->func;
> drmFreeDevice(&devinfo);
>
> + assert(info->drm_major == 3);
> + info->is_amdgpu = true;
> +
> /* Query hardware and driver information. */
> r = amdgpu_query_gpu_info(dev, amdinfo);
> if (r) {
> fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
> return false;
> }
>
> r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
> &device_info);
> if (r) {
> @@ -154,45 +157,45 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
> return false;
> }
>
> r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
> if (r) {
> fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
> return false;
> }
>
> - if (info->drm_major == 3 && info->drm_minor >= 17) {
> + if (info->drm_minor >= 17) {
> r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
> if (r) {
> fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
> return false;
> }
> }
>
> - if (info->drm_major == 3 && info->drm_minor >= 17) {
> + if (info->drm_minor >= 17) {
> r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
> if (r) {
> fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
> return false;
> }
> }
>
> - if (info->drm_major == 3 && info->drm_minor >= 17) {
> + if (info->drm_minor >= 17) {
> r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
> if (r) {
> fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
> return false;
> }
> }
>
> - if (info->drm_major == 3 && info->drm_minor >= 27) {
> + if (info->drm_minor >= 27) {
> r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
> if (r) {
> fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
> return false;
> }
> }
>
> r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
> &info->me_fw_version,
> &info->me_fw_feature);
> @@ -737,21 +740,21 @@ ac_get_raster_config(struct radeon_info *info,
> fprintf(stderr,
> "ac: Unknown GPU, using 0 for raster_config\n");
> raster_config = 0x00000000;
> raster_config_1 = 0x00000000;
> break;
> }
>
> /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
> * This decreases performance by up to 50% when the RB is the bottleneck.
> */
> - if (info->family == CHIP_KAVERI && info->drm_major == 2)
> + if (info->family == CHIP_KAVERI && !info->is_amdgpu)
> raster_config = 0x00000000;
>
> /* Fiji: Old kernels have incorrect tiling config. This decreases
> * RB performance by 25%. (it disables 1 RB in the second packer)
> */
> if (info->family == CHIP_FIJI &&
> info->cik_macrotile_mode_array[0] == 0x000000e8) {
> raster_config = 0x16000012;
> raster_config_1 = 0x0000002a;
> }
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index 2adc0e12f1b..2c67cec3ed5 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -92,20 +92,21 @@ struct radeon_info {
> bool has_hw_decode;
> bool uvd_enc_supported;
> uint32_t uvd_fw_version;
> uint32_t vce_fw_version;
> uint32_t vce_harvest_config;
>
> /* Kernel & winsys capabilities. */
> uint32_t drm_major; /* version */
> uint32_t drm_minor;
> uint32_t drm_patchlevel;
> + bool is_amdgpu;
> bool has_userptr;
> bool has_syncobj;
> bool has_syncobj_wait_for_submit;
> bool has_fence_to_handle;
> bool has_ctx_priority;
> bool has_local_buffers;
> bool kernel_flushes_hdp_before_ib;
> bool htile_cmask_support_1d_tiling;
> bool si_TA_CS_BC_BASE_ADDR_allowed;
> bool has_bo_metadata;
> diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
> index 2177cda0f4a..80d15599123 100644
> --- a/src/amd/vulkan/radv_debug.c
> +++ b/src/amd/vulkan/radv_debug.c
> @@ -104,28 +104,25 @@ radv_dump_mmapped_reg(struct radv_device *device, FILE *f, unsigned offset)
> if (ws->read_registers(ws, offset, 1, &value))
> ac_dump_reg(f, device->physical_device->rad_info.chip_class,
> offset, value, ~0);
> }
>
> static void
> radv_dump_debug_registers(struct radv_device *device, FILE *f)
> {
> struct radeon_info *info = &device->physical_device->rad_info;
>
> - if (info->drm_major == 2 && info->drm_minor < 42)
> - return; /* no radeon support */
> -
> fprintf(f, "Memory-mapped registers:\n");
> radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
>
> /* No other registers can be read on DRM < 3.1.0. */
> - if (info->drm_major < 3 || info->drm_minor < 1) {
> + if (info->drm_minor < 1) {
> fprintf(f, "\n");
> return;
> }
>
> radv_dump_mmapped_reg(device, f, R_008008_GRBM_STATUS2);
> radv_dump_mmapped_reg(device, f, R_008014_GRBM_STATUS_SE0);
> radv_dump_mmapped_reg(device, f, R_008018_GRBM_STATUS_SE1);
> radv_dump_mmapped_reg(device, f, R_008038_GRBM_STATUS_SE2);
> radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
> radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
> diff --git a/src/gallium/drivers/r600/r600_buffer_common.c b/src/gallium/drivers/r600/r600_buffer_common.c
> index 17a8c3a596f..047394a5297 100644
> --- a/src/gallium/drivers/r600/r600_buffer_common.c
> +++ b/src/gallium/drivers/r600/r600_buffer_common.c
> @@ -119,22 +119,21 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
> /* fall through */
> case PIPE_USAGE_STAGING:
> /* Transfers are likely to occur more often with these
> * resources. */
> res->domains = RADEON_DOMAIN_GTT;
> break;
> case PIPE_USAGE_DYNAMIC:
> /* Older kernels didn't always flush the HDP cache before
> * CS execution
> */
> - if (rscreen->info.drm_major == 2 &&
> - rscreen->info.drm_minor < 40) {
> + if (rscreen->info.drm_minor < 40) {
> res->domains = RADEON_DOMAIN_GTT;
> res->flags |= RADEON_FLAG_GTT_WC;
> break;
> }
> /* fall through */
> case PIPE_USAGE_DEFAULT:
> case PIPE_USAGE_IMMUTABLE:
> default:
> /* Not listing GTT here improves performance in some
> * apps. */
> @@ -147,22 +146,21 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
> res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
> PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
> /* Use GTT for all persistent mappings with older
> * kernels, because they didn't always flush the HDP
> * cache before CS execution.
> *
> * Write-combined CPU mappings are fine, the kernel
> * ensures all CPU writes finish before the GPU
> * executes a command stream.
> */
> - if (rscreen->info.drm_major == 2 &&
> - rscreen->info.drm_minor < 40)
> + if (rscreen->info.drm_minor < 40)
> res->domains = RADEON_DOMAIN_GTT;
> }
>
> /* Tiled textures are unmappable. Always put them in VRAM. */
> if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
> res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
> res->domains = RADEON_DOMAIN_VRAM;
> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
> RADEON_FLAG_GTT_WC;
> }
> diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
> index 1aa673c0a53..2a14aa05ca5 100644
> --- a/src/gallium/drivers/r600/r600_pipe.c
> +++ b/src/gallium/drivers/r600/r600_pipe.c
> @@ -315,21 +315,21 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
> case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
> case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
> case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
> return 1;
>
> case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
> /* Optimal number for good TexSubImage performance on Polaris10. */
> return 64 * 1024 * 1024;
>
> case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
> - return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
> + return rscreen->b.info.drm_minor >= 43;
>
> case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
> return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
>
> case PIPE_CAP_COMPUTE:
> return rscreen->b.chip_class > R700;
>
> case PIPE_CAP_TGSI_TEXCOORD:
> return 0;
>
> diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c
> index 5177ff4e1c6..566c63cc4d8 100644
> --- a/src/gallium/drivers/r600/r600_pipe_common.c
> +++ b/src/gallium/drivers/r600/r600_pipe_common.c
> @@ -338,62 +338,26 @@ void r600_postflush_resume_features(struct r600_common_context *ctx)
> if (ctx->streamout.suspended) {
> ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
> r600_streamout_buffers_dirty(ctx);
> }
>
> /* resume queries */
> if (!LIST_IS_EMPTY(&ctx->active_queries))
> r600_resume_queries(ctx);
> }
>
> -static void r600_add_fence_dependency(struct r600_common_context *rctx,
> - struct pipe_fence_handle *fence)
> -{
> - struct radeon_winsys *ws = rctx->ws;
> -
> - if (rctx->dma.cs)
> - ws->cs_add_fence_dependency(rctx->dma.cs, fence, 0);
> - ws->cs_add_fence_dependency(rctx->gfx.cs, fence, 0);
> -}
> -
> static void r600_fence_server_sync(struct pipe_context *ctx,
> struct pipe_fence_handle *fence)
> {
> - struct r600_common_context *rctx = (struct r600_common_context *)ctx;
> - struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
> -
> - /* Only amdgpu needs to handle fence dependencies (for fence imports).
> - * radeon synchronizes all rings by default and will not implement
> + /* radeon synchronizes all rings by default and will not implement
> * fence imports.
> */
> - if (rctx->screen->info.drm_major == 2)
> - return;
> -
> - /* Only imported fences need to be handled by fence_server_sync,
> - * because the winsys handles synchronizations automatically for BOs
> - * within the process.
> - *
> - * Simply skip unflushed fences here, and the winsys will drop no-op
> - * dependencies (i.e. dependencies within the same ring).
> - */
> - if (rfence->gfx_unflushed.ctx)
> - return;
> -
> - /* All unflushed commands will not start execution before
> - * this fence dependency is signalled.
> - *
> - * Should we flush the context to allow more GPU parallelism?
> - */
> - if (rfence->sdma)
> - r600_add_fence_dependency(rctx, rfence->sdma);
> - if (rfence->gfx)
> - r600_add_fence_dependency(rctx, rfence->gfx);
> }
>
> static void r600_flush_from_st(struct pipe_context *ctx,
> struct pipe_fence_handle **fence,
> unsigned flags)
> {
> struct pipe_screen *screen = ctx->screen;
> struct r600_common_context *rctx = (struct r600_common_context *)ctx;
> struct radeon_winsys *ws = rctx->ws;
> struct pipe_fence_handle *gfx_fence = NULL;
> @@ -1220,26 +1184,22 @@ static void r600_query_memory_info(struct pipe_screen *screen,
> info->avail_device_memory =
> vram_usage <= info->total_device_memory ?
> info->total_device_memory - vram_usage : 0;
> info->avail_staging_memory =
> gtt_usage <= info->total_staging_memory ?
> info->total_staging_memory - gtt_usage : 0;
>
> info->device_memory_evicted =
> ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
>
> - if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
> - info->nr_device_memory_evictions =
> - ws->query_value(ws, RADEON_NUM_EVICTIONS);
> - else
> - /* Just return the number of evicted 64KB pages. */
> - info->nr_device_memory_evictions = info->device_memory_evicted / 64;
> + /* Just return the number of evicted 64KB pages. */
> + info->nr_device_memory_evictions = info->device_memory_evicted / 64;
> }
>
> struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
> const struct pipe_resource *templ)
> {
> if (templ->target == PIPE_BUFFER) {
> return r600_buffer_create(screen, templ, 256);
> } else {
> return r600_texture_create(screen, templ);
> }
> diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
> index e7ef34ba412..ed2226293dd 100644
> --- a/src/gallium/drivers/r600/r600_query.c
> +++ b/src/gallium/drivers/r600/r600_query.c
> @@ -2024,21 +2024,21 @@ static const struct pipe_driver_query_info r600_driver_query_list[] = {
> X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
> X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
> };
>
> #undef X
> #undef XG
> #undef XFULL
>
> static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
> {
> - if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
> + if (rscreen->info.drm_minor >= 42)
> return ARRAY_SIZE(r600_driver_query_list);
> else
> return ARRAY_SIZE(r600_driver_query_list) - 25;
> }
>
> static int r600_get_driver_query_info(struct pipe_screen *screen,
> unsigned index,
> struct pipe_driver_query_info *info)
> {
> struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
> diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
> index 497da0c3dfa..12812e0e396 100644
> --- a/src/gallium/drivers/r600/r600_texture.c
> +++ b/src/gallium/drivers/r600/r600_texture.c
> @@ -755,21 +755,21 @@ void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
> static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
> struct r600_texture *rtex)
> {
> unsigned cl_width, cl_height, width, height;
> unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
> unsigned num_pipes = rscreen->info.num_tile_pipes;
>
> rtex->surface.htile_size = 0;
>
> if (rscreen->chip_class <= EVERGREEN &&
> - rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
> + rscreen->info.drm_minor < 26)
> return;
>
> /* HW bug on R6xx. */
> if (rscreen->chip_class == R600 &&
> (rtex->resource.b.b.width0 > 7680 ||
> rtex->resource.b.b.height0 > 7680))
> return;
>
> switch (num_pipes) {
> case 1:
> diff --git a/src/gallium/drivers/r600/radeon_uvd.c b/src/gallium/drivers/r600/radeon_uvd.c
> index 5568f2138e4..7f853446b14 100644
> --- a/src/gallium/drivers/r600/radeon_uvd.c
> +++ b/src/gallium/drivers/r600/radeon_uvd.c
> @@ -1307,22 +1307,21 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
> default:
> break;
> }
>
>
> dec = CALLOC_STRUCT(ruvd_decoder);
>
> if (!dec)
> return NULL;
>
> - if (info.drm_major < 3)
> - dec->use_legacy = true;
> + dec->use_legacy = true;
>
> dec->base = *templ;
> dec->base.context = context;
> dec->base.width = width;
> dec->base.height = height;
>
> dec->base.destroy = ruvd_destroy;
> dec->base.begin_frame = ruvd_begin_frame;
> dec->base.decode_macroblock = ruvd_decode_macroblock;
> dec->base.decode_bitstream = ruvd_decode_bitstream;
> diff --git a/src/gallium/drivers/r600/radeon_vce.c b/src/gallium/drivers/r600/radeon_vce.c
> index e38b927b1d4..4dae56f95ce 100644
> --- a/src/gallium/drivers/r600/radeon_vce.c
> +++ b/src/gallium/drivers/r600/radeon_vce.c
> @@ -404,24 +404,21 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
>
> } else if (!rvce_is_fw_version_supported(rscreen)) {
> RVID_ERR("Unsupported VCE fw version loaded!\n");
> return NULL;
> }
>
> enc = CALLOC_STRUCT(rvce_encoder);
> if (!enc)
> return NULL;
>
> - if (rscreen->info.drm_major == 3)
> - enc->use_vm = true;
> - if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
> - rscreen->info.drm_major == 3)
> + if (rscreen->info.drm_minor >= 42)
> enc->use_vui = true;
>
> enc->base = *templ;
> enc->base.context = context;
>
> enc->base.destroy = rvce_destroy;
> enc->base.begin_frame = rvce_begin_frame;
> enc->base.encode_bitstream = rvce_encode_bitstream;
> enc->base.end_frame = rvce_end_frame;
> enc->base.flush = rvce_flush;
> diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
> index ca066e89823..6c03c123293 100644
> --- a/src/gallium/drivers/radeon/radeon_uvd.c
> +++ b/src/gallium/drivers/radeon/radeon_uvd.c
> @@ -1243,21 +1243,21 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
> default:
> break;
> }
>
>
> dec = CALLOC_STRUCT(ruvd_decoder);
>
> if (!dec)
> return NULL;
>
> - if (sctx->screen->info.drm_major < 3)
> + if (!sctx->screen->info.is_amdgpu)
> dec->use_legacy = true;
>
> dec->base = *templ;
> dec->base.context = context;
> dec->base.width = width;
> dec->base.height = height;
>
> dec->base.destroy = ruvd_destroy;
> dec->base.begin_frame = ruvd_begin_frame;
> dec->base.decode_macroblock = ruvd_decode_macroblock;
> diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
> index 94df06e88c6..264b96b83c9 100644
> --- a/src/gallium/drivers/radeon/radeon_vce.c
> +++ b/src/gallium/drivers/radeon/radeon_vce.c
> @@ -403,24 +403,24 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
>
> } else if (!si_vce_is_fw_version_supported(sscreen)) {
> RVID_ERR("Unsupported VCE fw version loaded!\n");
> return NULL;
> }
>
> enc = CALLOC_STRUCT(rvce_encoder);
> if (!enc)
> return NULL;
>
> - if (sscreen->info.drm_major == 3)
> + if (sscreen->info.is_amdgpu)
> enc->use_vm = true;
> - if ((sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42) ||
> - sscreen->info.drm_major == 3)
> + if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
> + sscreen->info.is_amdgpu)
> enc->use_vui = true;
> if (sscreen->info.family >= CHIP_TONGA &&
> sscreen->info.family != CHIP_STONEY &&
> sscreen->info.family != CHIP_POLARIS11 &&
> sscreen->info.family != CHIP_POLARIS12 &&
> sscreen->info.family != CHIP_VEGAM)
> enc->dual_pipe = true;
> /* TODO enable B frame with dual instance */
> if ((sscreen->info.family >= CHIP_TONGA) &&
> (templ->max_references == 1) &&
> diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
> index 76705937b65..614d00b4667 100644
> --- a/src/gallium/drivers/radeonsi/si_buffer.c
> +++ b/src/gallium/drivers/radeonsi/si_buffer.c
> @@ -148,21 +148,21 @@ void si_init_resource_fields(struct si_screen *sscreen,
> * cache before CS execution.
> *
> * Write-combined CPU mappings are fine, the kernel
> * ensures all CPU writes finish before the GPU
> * executes a command stream.
> *
> * radeon doesn't have good BO move throttling, so put all
> * persistent buffers into GTT to prevent VRAM CPU page faults.
> */
> if (!sscreen->info.kernel_flushes_hdp_before_ib ||
> - sscreen->info.drm_major == 2)
> + !sscreen->info.is_amdgpu)
> res->domains = RADEON_DOMAIN_GTT;
> }
>
> /* Tiled textures are unmappable. Always put them in VRAM. */
> if ((res->b.b.target != PIPE_BUFFER && !tex->surface.is_linear) ||
> res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
> res->domains = RADEON_DOMAIN_VRAM;
> res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
> RADEON_FLAG_GTT_WC;
> }
> diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c
> index 165e95c4ce5..4177eed45f7 100644
> --- a/src/gallium/drivers/radeonsi/si_debug.c
> +++ b/src/gallium/drivers/radeonsi/si_debug.c
> @@ -293,21 +293,21 @@ static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f,
>
> static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
> {
> if (!sctx->screen->info.has_read_registers_query)
> return;
>
> fprintf(f, "Memory-mapped registers:\n");
> si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
>
> /* No other registers can be read on DRM < 3.1.0. */
> - if (sctx->screen->info.drm_major < 3 ||
> + if (!sctx->screen->info.is_amdgpu ||
> sctx->screen->info.drm_minor < 1) {
> fprintf(f, "\n");
> return;
> }
>
> si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
> si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
> si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
> si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
> si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
> diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
> index 40a54b34c4f..c1bddca1a66 100644
> --- a/src/gallium/drivers/radeonsi/si_get.c
> +++ b/src/gallium/drivers/radeonsi/si_get.c
> @@ -621,21 +621,21 @@ static int si_get_video_param(struct pipe_screen *screen,
> profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
> else if (sscreen->info.family >= CHIP_CARRIZO)
> return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
> return false;
> case PIPE_VIDEO_FORMAT_JPEG:
> if (sscreen->info.family == CHIP_RAVEN ||
> sscreen->info.family == CHIP_RAVEN2)
> return true;
> if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
> return false;
> - if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
> + if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
> RVID_ERR("No MJPEG support for the kernel version\n");
> return false;
> }
> return true;
> case PIPE_VIDEO_FORMAT_VP9:
> if (sscreen->info.family < CHIP_RAVEN)
> return false;
> return true;
> default:
> return false;
> @@ -913,21 +913,21 @@ static void si_query_memory_info(struct pipe_screen *screen,
> info->avail_device_memory =
> vram_usage <= info->total_device_memory ?
> info->total_device_memory - vram_usage : 0;
> info->avail_staging_memory =
> gtt_usage <= info->total_staging_memory ?
> info->total_staging_memory - gtt_usage : 0;
>
> info->device_memory_evicted =
> ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
>
> - if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
> + if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
> info->nr_device_memory_evictions =
> ws->query_value(ws, RADEON_NUM_EVICTIONS);
> else
> /* Just return the number of evicted 64KB pages. */
> info->nr_device_memory_evictions = info->device_memory_evicted / 64;
> }
>
> static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
> {
> struct si_screen *sscreen = (struct si_screen*)pscreen;
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
> index 1faaa22ab0d..d5155622580 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -666,21 +666,21 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
>
> /* When shaders are logged to stderr, asynchronous compilation is
> * disabled too. */
> if (sscreen->debug_flags & DBG_ALL_SHADERS)
> return ctx;
>
> /* Use asynchronous flushes only on amdgpu, since the radeon
> * implementation for fence_server_sync is incomplete. */
> return threaded_context_create(ctx, &sscreen->pool_transfers,
> si_replace_buffer_storage,
> - sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
> + sscreen->info.is_amdgpu ? si_create_fence : NULL,
> &((struct si_context*)ctx)->tc);
> }
>
> /*
> * pipe_screen
> */
> static void si_destroy_screen(struct pipe_screen* pscreen)
> {
> struct si_screen *sscreen = (struct si_screen *)pscreen;
> struct si_shader_part *parts[] = {
> @@ -1053,21 +1053,21 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
> } else {
> assert(offchip_granularity == V_03093C_X_8K_DWORDS);
> sscreen->vgt_hs_offchip_param =
> S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
> }
>
> /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
> * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
> * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
> sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
> - sscreen->info.drm_major == 3;
> + sscreen->info.is_amdgpu;
>
> sscreen->has_distributed_tess =
> sscreen->info.chip_class >= GFX8 &&
> sscreen->info.max_se >= 2;
>
> sscreen->has_draw_indirect_multi =
> (sscreen->info.family >= CHIP_POLARIS10) ||
> (sscreen->info.chip_class == GFX8 &&
> sscreen->info.pfp_fw_version >= 121 &&
> sscreen->info.me_fw_version >= 87) ||
> diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
> index fd0e07904aa..a2b5937d69f 100644
> --- a/src/gallium/drivers/radeonsi/si_query.c
> +++ b/src/gallium/drivers/radeonsi/si_query.c
> @@ -1812,21 +1812,21 @@ static struct pipe_driver_query_info si_driver_query_list[] = {
> X("pd-num-prims-ineligible", PD_NUM_PRIMS_INELIGIBLE,UINT64, AVERAGE),
> };
>
> #undef X
> #undef XG
> #undef XFULL
>
> static unsigned si_get_num_queries(struct si_screen *sscreen)
> {
> /* amdgpu */
> - if (sscreen->info.drm_major == 3) {
> + if (sscreen->info.is_amdgpu) {
> if (sscreen->info.chip_class >= GFX8)
> return ARRAY_SIZE(si_driver_query_list);
> else
> return ARRAY_SIZE(si_driver_query_list) - 7;
> }
>
> /* radeon */
> if (sscreen->info.has_read_registers_query) {
> if (sscreen->info.chip_class == GFX7)
> return ARRAY_SIZE(si_driver_query_list) - 6;
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 6f98cee8ebd..fc2e282b82c 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -4984,21 +4984,21 @@ static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *p
>
> static void si_init_config(struct si_context *sctx)
> {
> struct si_screen *sscreen = sctx->screen;
> uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
> bool has_clear_state = sscreen->has_clear_state;
> struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
>
> /* GFX6, radeon kernel disabled CLEAR_STATE. */
> assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
> - sscreen->info.drm_major != 3);
> + !sscreen->info.is_amdgpu);
>
> if (!pm4)
> return;
>
> si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
> si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
> si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
> si_pm4_cmd_end(pm4, false);
>
> if (has_clear_state) {
> diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> index 7aa45b52639..c30b40376a2 100644
> --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
> @@ -159,20 +159,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
> version->version_major,
> version->version_minor,
> version->version_patchlevel);
> drmFreeVersion(version);
> return false;
> }
>
> ws->info.drm_major = version->version_major;
> ws->info.drm_minor = version->version_minor;
> ws->info.drm_patchlevel = version->version_patchlevel;
> + ws->info.is_amdgpu = false;
> drmFreeVersion(version);
>
> /* Get PCI ID. */
> if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
> &ws->info.pci_id))
> return false;
>
> /* Check PCI ID. */
> switch (ws->info.pci_id) {
> #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
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