[Mesa-dev] [PATCH] radv: implement compressed FMASK texture reads with RADV_PERFTEST=tccompatcmask
Bas Nieuwenhuizen
bas at basnieuwenhuizen.nl
Mon Jun 17 10:24:04 UTC 2019
On Thu, Jun 13, 2019, 3:42 PM Samuel Pitoiset <samuel.pitoiset at gmail.com>
wrote:
> This allows us to disable the FMASK decompress pass when
> transitioning from CB writes to shader reads.
>
> This will likely be improved and enabled by default in the future.
>
> No CTS regressions on GFX8 but a few number of multisample CTS
> failures on GFX9 (they look related to the small hint).
>
> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 9 ++++++
> src/amd/vulkan/radv_debug.h | 1 +
> src/amd/vulkan/radv_device.c | 15 ++++++++++
> src/amd/vulkan/radv_image.c | 42 +++++++++++++++++++++++++++
> src/amd/vulkan/radv_meta.h | 26 +++++++++++++++++
> src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
> src/amd/vulkan/radv_private.h | 10 +++++++
> 7 files changed, 104 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 2fd5f8b7a07..bf208899887 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1254,6 +1254,15 @@ radv_emit_fb_color_state(struct radv_cmd_buffer
> *cmd_buffer,
> cb_color_info &= C_028C70_DCC_ENABLE;
> }
>
> + if (radv_image_is_tc_compat_cmask(image) &&
> + (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
> + radv_is_dcc_decompress_pipeline(cmd_buffer))) {
> + /* If this bit is set, the FMASK decompression operation
> + * doesn't occur (DCC_COMPRESS also implies
> FMASK_DECOMPRESS).
> + */
> + cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
> + }
> +
> if (cmd_buffer->device->physical_device->rad_info.chip_class >=
> GFX9) {
> radeon_set_context_reg_seq(cmd_buffer->cs,
> R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
> radeon_emit(cmd_buffer->cs, cb->cb_color_base);
> diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
> index 652a3b677d2..29793e549ce 100644
> --- a/src/amd/vulkan/radv_debug.h
> +++ b/src/amd/vulkan/radv_debug.h
> @@ -61,6 +61,7 @@ enum {
> RADV_PERFTEST_OUT_OF_ORDER = 0x8,
> RADV_PERFTEST_DCC_MSAA = 0x10,
> RADV_PERFTEST_BO_LIST = 0x20,
> + RADV_PERFTEST_TC_COMPAT_CMASK = 0x40,
> };
>
> bool
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 3b69e457496..b75ce59dfc3 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -479,6 +479,7 @@ static const struct debug_control
> radv_perftest_options[] = {
> {"localbos", RADV_PERFTEST_LOCAL_BOS},
> {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
> {"bolist", RADV_PERFTEST_BO_LIST},
> + {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
> {NULL, 0}
> };
>
> @@ -4389,6 +4390,20 @@ radv_initialise_color_surface(struct radv_device
> *device,
> unsigned fmask_bankh =
> util_logbase2(iview->image->fmask.bank_height);
> cb->cb_color_attrib |=
> S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
> }
> +
> + if (radv_image_is_tc_compat_cmask(iview->image)) {
> + /* Allow the texture block to read FMASK directly
> + * without decompressing it. This bit must be
> cleared
> + * when performing FMASK_DECOMPRESS or
> DCC_COMPRESS,
> + * otherwise the operation doesn't happen.
> + */
> + cb->cb_color_info |=
> S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
> +
> + /* Set CMASK into a tiling format that allows the
> + * texture block to read it.
> + */
> + cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
> + }
> }
>
> if (radv_image_has_cmask(iview->image) &&
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index d8dc2dfabde..c58c08fca59 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -219,6 +219,29 @@ radv_use_dcc_for_image(struct radv_device *device,
> return true;
> }
>
> +static bool
> +radv_use_tc_compat_cmask_for_image(struct radv_device *device,
> + struct radv_image *image)
> +{
+ if (!(device->instance->perftest_flags &
> RADV_PERFTEST_TC_COMPAT_CMASK))
> + return false;
> +
> + /* TC-compat CMASK is only available for GFX8+. */
> + if (device->physical_device->rad_info.chip_class < GFX8)
> + return false;
> +
> + if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
> + return false;
> +
> + if (radv_image_has_dcc(image))
> + return false;
> +
> + if (!radv_image_has_cmask(image))
> + return false;
> +
> + return true;
> +}
> +
> static void
> radv_prefill_surface_from_metadata(struct radv_device *device,
> struct radeon_surf *surface,
> @@ -726,11 +749,26 @@ si_make_texture_descriptor(struct radv_device
> *device,
>
> S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
> fmask_state[5] |=
> S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned)
> |
>
> S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
> +
> + if (radv_image_is_tc_compat_cmask(image)) {
> + va = gpu_address + image->offset +
> image->cmask.offset;
> +
> + fmask_state[5] |=
> S_008F24_META_DATA_ADDRESS(va >> 40);
> + fmask_state[6] |=
> S_008F28_COMPRESSION_EN(1);
> + fmask_state[7] |= va >> 8;
> + }
> } else {
> fmask_state[3] |=
> S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
> fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
>
> S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
> fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
> +
> + if (radv_image_is_tc_compat_cmask(image)) {
> + va = gpu_address + image->offset +
> image->cmask.offset;
> +
> + fmask_state[6] |=
> S_008F28_COMPRESSION_EN(1);
> + fmask_state[7] |= va >> 8;
> + }
> }
> } else if (fmask_state)
> memset(fmask_state, 0, 8 * 4);
> @@ -1034,6 +1072,7 @@ radv_image_can_enable_fmask(struct radv_image *image)
> return image->info.samples > 1 &&
> vk_format_is_color(image->vk_format);
> }
>
> +
>
spurious change?
> static inline bool
> radv_image_can_enable_htile(struct radv_image *image)
> {
> @@ -1158,6 +1197,9 @@ radv_image_create(VkDevice _device,
> /* Try to enable FMASK for multisampled images. */
> if (radv_image_can_enable_fmask(image)) {
> radv_image_alloc_fmask(device, image);
> +
> + if (radv_use_tc_compat_cmask_for_image(device,
> image))
> + image->tc_compatible_cmask = true;
> } else {
> /* Otherwise, try to enable HTILE for depth
> surfaces. */
> if (radv_image_can_enable_htile(image) &&
> diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
> index 59b9121cf39..2aa2d15770b 100644
> --- a/src/amd/vulkan/radv_meta.h
> +++ b/src/amd/vulkan/radv_meta.h
> @@ -221,6 +221,32 @@ uint32_t radv_clear_htile(struct radv_cmd_buffer
> *cmd_buffer,
> struct radv_image *image,
> const VkImageSubresourceRange *range, uint32_t
> value);
>
> +/**
> + * Return whether the bound pipeline is the FMASK decompress pass.
> + */
> +static inline bool
> +radv_is_fmask_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer)
> +{
> + struct radv_meta_state *meta_state =
> &cmd_buffer->device->meta_state;
> + struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
> +
> + return radv_pipeline_to_handle(pipeline) ==
> + meta_state->fast_clear_flush.fmask_decompress_pipeline;
> +}
> +
> +/**
> + * Return whether the bound pipeline is the DCC decompress pass.
> + */
> +static inline bool
> +radv_is_dcc_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer)
> +{
> + struct radv_meta_state *meta_state =
> &cmd_buffer->device->meta_state;
> + struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
> +
> + return radv_pipeline_to_handle(pipeline) ==
> + meta_state->fast_clear_flush.dcc_decompress_pipeline;
> +}
> +
> /* common nir builder helpers */
> #include "nir/nir_builder.h"
>
> diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
> b/src/amd/vulkan/radv_meta_fast_clear.c
> index 8f97c1a8f15..94c83dc96be 100644
> --- a/src/amd/vulkan/radv_meta_fast_clear.c
> +++ b/src/amd/vulkan/radv_meta_fast_clear.c
> @@ -595,7 +595,7 @@ radv_emit_color_decompress(struct radv_cmd_buffer
> *cmd_buffer,
>
> if (decompress_dcc && radv_image_has_dcc(image)) {
> pipeline =
> cmd_buffer->device->meta_state.fast_clear_flush.dcc_decompress_pipeline;
> - } else if (radv_image_has_fmask(image)) {
> + } else if (radv_image_has_fmask(image) &&
> !image->tc_compatible_cmask) {
> pipeline =
> cmd_buffer->device->meta_state.fast_clear_flush.fmask_decompress_pipeline;
> } else {
> pipeline =
> cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline;
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 8f2e80b3017..1a7797b55e1 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1555,6 +1555,7 @@ struct radv_image {
> uint64_t dcc_offset;
> uint64_t htile_offset;
> bool tc_compatible_htile;
> + bool tc_compatible_cmask;
>
> struct radv_fmask_info fmask;
> struct radv_cmask_info cmask;
> @@ -1628,6 +1629,15 @@ radv_image_has_dcc(const struct radv_image *image)
> return image->planes[0].surface.dcc_size;
> }
>
> +/**
> + * Return whether the image is TC-compatible CMASK.
> + */
> +static inline bool
> +radv_image_is_tc_compat_cmask(const struct radv_image *image)
> +{
> + return radv_image_has_fmask(image) && image->tc_compatible_cmask;
> +}
> +
> /**
> * Return whether DCC metadata is enabled for a level.
> */
> --
> 2.22.0
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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