[Mesa-dev] [PATCH] radeon/vcn: enable rate control for hevc encoding

[boyuan.zhang at amd.com]

From: Boyuan Zhang <boyuan.zhang at amd.com>

Set cu_qp_delta_enable_flag on when rate control is enabled, and it
off when no rate control is disabled (constant qp).

Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 3302ed7524..e4b9162034 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -687,7 +687,13 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
 	radeon_enc_code_se(enc, 0x0);
 	radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
 	radeon_enc_code_fixed_bits(enc, 0x0, 1);
-	radeon_enc_code_fixed_bits(enc, 0x0, 1);
+	if (enc->enc_pic.rc_session_init.rate_control_method ==
+		RENC_UVD_RATE_CONTROL_METHOD_NONE)
+		radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+	else {
+		radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+		radeon_uvd_enc_code_ue(enc, 0x0);
+	}
 	radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
 	radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
 	radeon_enc_code_fixed_bits(enc, 0x0, 1);
-- 
2.17.1