[Mesa-dev] [PATCH v2 1/5] nir/lower_tex: Add a way to lower TXS(non-0-LOD) instructions

[Jason Ekstrand]

On Tue, Jun 18, 2019 at 2:38 AM Boris Brezillon <
boris.brezillon at collabora.com> wrote:

> The V3D driver has an open-coded solution for this, and we need the
> same thing for Panfrost, so let's add a generic way to lower TXS(LOD)
> into max(TXS(0) >> LOD, 1).
>
> Signed-off-by: Boris Brezillon <boris.brezillon at collabora.com>
> ---
> Changes in v2:
> * Use == 0 instead of !
> * Rework the minification logic as suggested by Jason
> * Assign cursor pos at the beginning of the function
> * Patch the LOD just after retrieving the old value
> ---
>  src/compiler/nir/nir.h           |  6 +++++
>  src/compiler/nir/nir_lower_tex.c | 46 ++++++++++++++++++++++++++++++++
>  2 files changed, 52 insertions(+)
>
> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
> index 4270df565111..8972b4af7480 100644
> --- a/src/compiler/nir/nir.h
> +++ b/src/compiler/nir/nir.h
> @@ -3426,6 +3426,12 @@ typedef struct nir_lower_tex_options {
>      */
>     bool lower_txd_clamp_if_sampler_index_not_lt_16;
>
> +   /**
> +    * If true, lower nir_texop_txs with a non-0-lod into nir_texop_txs
> with
> +    * 0-lod followed by a nir_ishr.
> +    */
> +   bool lower_txs_lod;
> +
>     /**
>      * If true, apply a .bagr swizzle on tg4 results to handle Broadcom's
>      * mixed-up tg4 locations.
> diff --git a/src/compiler/nir/nir_lower_tex.c
> b/src/compiler/nir/nir_lower_tex.c
> index 53719017a87f..6f82ca5f06db 100644
> --- a/src/compiler/nir/nir_lower_tex.c
> +++ b/src/compiler/nir/nir_lower_tex.c
> @@ -978,6 +978,47 @@ lower_tg4_offsets(nir_builder *b, nir_tex_instr *tex)
>     return true;
>  }
>
> +static bool
> +nir_lower_txs_lod(nir_builder *b, nir_tex_instr *tex)
> +{
> +   int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
> +   if (lod_idx < 0 ||
> +       (nir_src_is_const(tex->src[lod_idx].src) &&
> +        nir_src_as_int(tex->src[lod_idx].src) == 0))
> +      return false;
> +
> +   unsigned dest_size = nir_tex_instr_dest_size(tex);
> +
> +   b->cursor = nir_before_instr(&tex->instr);
> +   nir_ssa_def *lod = nir_ssa_for_src(b, tex->src[lod_idx].src, 1);
> +
> +   /* Replace the non-0-LOD in the initial TXS operation by a 0-LOD. */
> +   nir_instr_rewrite_src(&tex->instr, &tex->src[lod_idx].src,
> +                         nir_src_for_ssa(nir_imm_int(b, 0)));
> +
> +   /* TXS(LOD) = max(TXS(0) >> LOD, 1) */
> +   b->cursor = nir_after_instr(&tex->instr);
> +   nir_ssa_def *minified = nir_imax(b, nir_ushr(b, &tex->dest.ssa, lod),
> +                                    nir_imm_int(b, 1));
> +
> +   /* Make sure the component encoding the array size (if any) is not
> +    * minified.
> +    */
> +   if (tex->is_array) {
> +      nir_ssa_def *comp[3];
>

Mind throwing in a quick assert?

assert(dest_size <= ARRAY_SIZE(comp));

With that added,

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>


> +
> +      for (unsigned i = 0; i < dest_size - 1; i++)
> +         comp[i] = nir_channel(b, minified, i);
> +
> +      comp[dest_size - 1] = nir_channel(b, &tex->dest.ssa, dest_size - 1);
> +      minified = nir_vec(b, comp, dest_size);
> +   }
> +
> +   nir_ssa_def_rewrite_uses_after(&tex->dest.ssa,
> nir_src_for_ssa(minified),
> +                                  minified->parent_instr);
> +   return true;
> +}
> +
>  static bool
>  nir_lower_tex_block(nir_block *block, nir_builder *b,
>                      const nir_lower_tex_options *options)
> @@ -1132,6 +1173,11 @@ nir_lower_tex_block(nir_block *block, nir_builder
> *b,
>           continue;
>        }
>
> +      if (options->lower_txs_lod && tex->op == nir_texop_txs) {
> +         progress |= nir_lower_txs_lod(b, tex);
> +         continue;
> +      }
> +
>        /* has to happen after all the other lowerings as the original tg4
> gets
>         * replaced by 4 tg4 instructions.
>         */
> --
> 2.20.1
>
>
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