[Mesa-dev] [PATCH 7/8] radeonsi: fix AMD_DEBUG=nofmask
Marek Olšák
maraeo at gmail.com
Thu Jun 20 04:19:40 UTC 2019
From: Marek Olšák <marek.olsak at amd.com>
---
src/gallium/drivers/radeonsi/si_clear.c | 6 +++++-
.../drivers/radeonsi/si_shader_tgsi_mem.c | 8 +++++---
src/gallium/drivers/radeonsi/si_state.c | 16 ++++++++--------
src/gallium/drivers/radeonsi/si_texture.c | 4 ++--
4 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index d0094031a95..60daff383cb 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -30,21 +30,25 @@
#include "util/u_surface.h"
enum {
SI_CLEAR = SI_SAVE_FRAGMENT_STATE,
SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
};
static void si_alloc_separate_cmask(struct si_screen *sscreen,
struct si_texture *tex)
{
- if (tex->cmask_buffer || !tex->surface.cmask_size)
+ /* CMASK for MSAA is allocated in advance or always disabled
+ * by "nofmask" option.
+ */
+ if (tex->cmask_buffer || !tex->surface.cmask_size ||
+ tex->buffer.b.b.nr_samples >= 2)
return;
tex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
tex->surface.cmask_size,
tex->surface.cmask_alignment);
if (tex->cmask_buffer == NULL)
return;
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index a2e6a47cba3..cd5083f26d7 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -1527,22 +1527,23 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
else if (opcode == TGSI_OPCODE_TXF) {
if (target == TGSI_TEXTURE_2D_MSAA) {
/* No LOD, but move sample index into the right place. */
args.coords[2] = args.coords[3];
} else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
args.lod = args.coords[3];
}
}
- if (target == TGSI_TEXTURE_2D_MSAA ||
- target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
+ if ((target == TGSI_TEXTURE_2D_MSAA ||
+ target == TGSI_TEXTURE_2D_ARRAY_MSAA) &&
+ !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
target == TGSI_TEXTURE_2D_ARRAY_MSAA);
}
if (opcode == TGSI_OPCODE_TXF ||
opcode == TGSI_OPCODE_TXF_LZ) {
/* add tex offsets */
if (inst->Texture.NumOffsets) {
const struct tgsi_texture_offset *off = inst->TexOffsets;
@@ -1727,21 +1728,22 @@ static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action,
if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
/* Get the current render target layer index. */
if (ctx->shader->key.mono.u.ps.fbfetch_layered)
args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
args.coords[chan++] = si_get_sample_id(ctx);
- if (ctx->shader->key.mono.u.ps.fbfetch_msaa) {
+ if (ctx->shader->key.mono.u.ps.fbfetch_msaa &&
+ !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
ctx->shader->key.mono.u.ps.fbfetch_layered);
}
args.opcode = ac_image_load;
args.resource = image;
args.dmask = 0xf;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index fc2e282b82c..af21914a142 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2459,21 +2459,21 @@ static void si_initialize_color_surface(struct si_context *sctx,
color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
util_format_is_intensity(surf->base.format));
if (tex->buffer.b.b.nr_samples > 1) {
unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_fragments);
- if (tex->surface.fmask_size) {
+ if (tex->fmask_offset) {
color_info |= S_028C70_COMPRESSION(1);
unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
if (sctx->chip_class == GFX6) {
/* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
}
}
@@ -2710,21 +2710,21 @@ void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
if (tex->surface.has_stencil)
tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
}
unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
while (compressed_cb_mask) {
unsigned i = u_bit_scan(&compressed_cb_mask);
struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
struct si_texture *tex = (struct si_texture*)surf->texture;
- if (tex->surface.fmask_size)
+ if (tex->fmask_offset)
tex->dirty_level_mask |= 1 << surf->u.tex.level;
if (tex->dcc_gather_statistics)
tex->separate_dcc_dirty = true;
}
}
static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
{
for (int i = 0; i < state->nr_cbufs; ++i) {
struct si_surface *surf = NULL;
@@ -2895,21 +2895,21 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->framebuffer.spi_shader_col_format_blend |=
surf->spi_shader_col_format_blend << (i * 4);
sctx->framebuffer.spi_shader_col_format_blend_alpha |=
surf->spi_shader_col_format_blend_alpha << (i * 4);
if (surf->color_is_int8)
sctx->framebuffer.color_is_int8 |= 1 << i;
if (surf->color_is_int10)
sctx->framebuffer.color_is_int10 |= 1 << i;
- if (tex->surface.fmask_size)
+ if (tex->fmask_offset)
sctx->framebuffer.compressed_cb_mask |= 1 << i;
else
sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
/* Don't update nr_color_samples for non-AA buffers.
* (e.g. destination of MSAA resolve)
*/
if (tex->buffer.b.b.nr_samples >= 2 &&
tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
sctx->framebuffer.nr_color_samples =
@@ -3081,21 +3081,21 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
cb_color_base = tex->buffer.gpu_address >> 8;
cb_color_fmask = 0;
cb_color_cmask = tex->cmask_base_address_reg;
cb_dcc_base = 0;
cb_color_info = cb->cb_color_info | tex->cb_color_info;
cb_color_attrib = cb->cb_color_attrib;
if (cb->base.u.tex.level > 0)
cb_color_info &= C_028C70_FAST_CLEAR;
- if (tex->surface.fmask_size) {
+ if (tex->fmask_offset) {
cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
cb_color_fmask |= tex->surface.fmask_tile_swizzle;
}
/* Set up DCC. */
if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
bool is_msaa_resolve_dst = state->cbufs[0] &&
state->cbufs[0]->texture->nr_samples > 1 &&
state->cbufs[1] == &cb->base &&
state->cbufs[1]->texture->nr_samples <= 1;
@@ -3112,21 +3112,21 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
struct gfx9_surf_meta_flags meta;
if (tex->dcc_offset)
meta = tex->surface.u.gfx9.dcc;
else
meta = tex->surface.u.gfx9.cmask;
/* Set mutable surface parameters. */
cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
cb_color_base |= tex->surface.tile_swizzle;
- if (!tex->surface.fmask_size)
+ if (!tex->fmask_offset)
cb_color_fmask = cb_color_base;
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
S_028C74_RB_ALIGNED(meta.rb_aligned) |
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
@@ -3152,37 +3152,37 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
const struct legacy_surf_level *level_info =
&tex->surface.u.legacy.level[cb->base.u.tex.level];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
cb_color_base += level_info->offset >> 8;
/* Only macrotiled modes can set tile swizzle. */
if (level_info->mode == RADEON_SURF_MODE_2D)
cb_color_base |= tex->surface.tile_swizzle;
- if (!tex->surface.fmask_size)
+ if (!tex->fmask_offset)
cb_color_fmask = cb_color_base;
if (cb->base.u.tex.level > 0)
cb_color_cmask = cb_color_base;
if (cb_dcc_base)
cb_dcc_base += level_info->dcc_offset >> 8;
pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = level_info->nblk_x *
level_info->nblk_y / 64 - 1;
tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
- if (tex->surface.fmask_size) {
+ if (tex->fmask_offset) {
if (sctx->chip_class >= GFX7)
cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
} else {
/* This must be set for fast clear to work without FMASK. */
if (sctx->chip_class >= GFX7)
cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
@@ -3898,21 +3898,21 @@ si_make_texture_descriptor(struct si_screen *screen,
*/
if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
if (first_level == last_level)
state[7] = C_008F30_MAX_ANISO_RATIO;
else
state[7] = 0xffffffff;
}
}
/* Initialize the sampler view for FMASK. */
- if (tex->surface.fmask_size) {
+ if (tex->fmask_offset) {
uint32_t data_format, num_format;
va = tex->buffer.gpu_address + tex->fmask_offset;
#define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
if (screen->info.chip_class >= GFX9) {
data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
case FMASK(2,1):
num_format = V_008F14_IMG_FMASK_8_2_1;
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 27c977ac7d9..dd383635675 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1069,21 +1069,21 @@ void si_print_texture_info(struct si_screen *sscreen,
if (sscreen->info.chip_class >= GFX9) {
u_log_printf(log, " Surf: size=%"PRIu64", slice_size=%"PRIu64", "
"alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
tex->surface.surf_size,
tex->surface.u.gfx9.surf_slice_size,
tex->surface.surf_alignment,
tex->surface.u.gfx9.surf.swizzle_mode,
tex->surface.u.gfx9.surf.epitch,
tex->surface.u.gfx9.surf_pitch);
- if (tex->surface.fmask_size) {
+ if (tex->fmask_offset) {
u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", "
"alignment=%u, swmode=%u, epitch=%u\n",
tex->fmask_offset,
tex->surface.fmask_size,
tex->surface.fmask_alignment,
tex->surface.u.gfx9.fmask.swizzle_mode,
tex->surface.u.gfx9.fmask.epitch);
}
if (tex->cmask_buffer) {
@@ -1124,21 +1124,21 @@ void si_print_texture_info(struct si_screen *sscreen,
return;
}
u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
tex->surface.surf_size, tex->surface.surf_alignment, tex->surface.u.legacy.bankw,
tex->surface.u.legacy.bankh, tex->surface.u.legacy.num_banks, tex->surface.u.legacy.mtilea,
tex->surface.u.legacy.tile_split, tex->surface.u.legacy.pipe_config,
(tex->surface.flags & RADEON_SURF_SCANOUT) != 0);
- if (tex->surface.fmask_size)
+ if (tex->fmask_offset)
u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
tex->fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,
tex->surface.u.legacy.fmask.pitch_in_pixels,
tex->surface.u.legacy.fmask.bankh,
tex->surface.u.legacy.fmask.slice_tile_max,
tex->surface.u.legacy.fmask.tiling_index);
if (tex->cmask_buffer)
u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, alignment=%u, "
--
2.17.1
More information about the mesa-dev
mailing list