[Mesa-dev] [PATCH] radv: clear FMASK layers instead of the whole buffer on GFX8
Samuel Pitoiset
samuel.pitoiset at gmail.com
Mon Jun 24 10:18:01 UTC 2019
This reduces the size of fill operations needed to clear FMASK
for layered color textures.
GFX9 unsupported for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
src/amd/common/ac_surface.c | 1 +
src/amd/common/ac_surface.h | 1 +
src/amd/vulkan/radv_cmd_buffer.c | 7 ++++---
src/amd/vulkan/radv_image.c | 1 +
src/amd/vulkan/radv_meta.h | 3 ++-
src/amd/vulkan/radv_meta_clear.c | 22 ++++++++++++++++++----
src/amd/vulkan/radv_meta_fmask_expand.c | 2 +-
src/amd/vulkan/radv_private.h | 4 +++-
8 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 7b86cb1e1f2..03d3505df53 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -953,6 +953,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->u.legacy.fmask.tiling_index = fout.tileIndex;
surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
+ surf->u.legacy.fmask.slice_size = fout.sliceSize;
/* Compute tile swizzle for FMASK. */
if (config->info.fmask_surf_index &&
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 49f68f4fc92..aa93e917270 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -86,6 +86,7 @@ struct legacy_surf_fmask {
uint8_t tiling_index; /* max 31 */
uint8_t bankh; /* max 8 */
uint16_t pitch_in_pixels;
+ uint64_t slice_size;
};
struct legacy_surf_layout {
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 9b4d4528028..419be5842e8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4905,7 +4905,8 @@ static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
}
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range)
{
struct radv_cmd_state *state = &cmd_buffer->state;
static const uint32_t fmask_clear_values[4] = {
@@ -4920,7 +4921,7 @@ void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
+ state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
@@ -5010,7 +5011,7 @@ static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
}
if (radv_image_has_fmask(image)) {
- radv_initialize_fmask(cmd_buffer, image);
+ radv_initialize_fmask(cmd_buffer, image, range);
}
if (radv_dcc_enabled(image, range->baseMipLevel)) {
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index cf3f0eb1d55..ca007d1dd65 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -907,6 +907,7 @@ radv_image_get_fmask_info(struct radv_device *device,
out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
+ out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
out->alignment = image->planes[0].surface.fmask_alignment;
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 5880064ff30..30981f00790 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -214,7 +214,8 @@ void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value);
uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value);
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value);
uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value);
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index c3def76e957..0a9d9e76ca4 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1336,11 +1336,25 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
uint32_t
radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image, uint32_t value)
+ struct radv_image *image,
+ const VkImageSubresourceRange *range, uint32_t value)
{
- return radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->fmask.offset,
- image->fmask.size, value);
+ uint64_t offset = image->offset + image->fmask.offset;
+ uint64_t size;
+
+ /* MSAA images do not support mipmap levels. */
+ assert(range->baseMipLevel == 0 &&
+ radv_get_levelCount(image, range) == 1);
+
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* TODO: clear layers. */
+ size = image->fmask.size;
+ } else {
+ offset += image->fmask.slice_size * range->baseArrayLayer;
+ size = image->fmask.slice_size * radv_get_layerCount(image, range);
+ }
+
+ return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);
}
uint32_t
diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c
index e5d0868aab5..a8f5e0cc4c1 100644
--- a/src/amd/vulkan/radv_meta_fmask_expand.c
+++ b/src/amd/vulkan/radv_meta_fmask_expand.c
@@ -172,7 +172,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
RADV_CMD_FLAG_INV_GLOBAL_L2;
/* Re-initialize FMASK in fully expanded mode. */
- radv_initialize_fmask(cmd_buffer, image);
+ radv_initialize_fmask(cmd_buffer, image, subresourceRange);
}
void radv_device_finish_meta_fmask_expand_state(struct radv_device *device)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1249ad0445d..fd7baa5f5b5 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1555,6 +1555,7 @@ struct radv_fmask_info {
unsigned slice_tile_max;
unsigned tile_mode_index;
unsigned tile_swizzle;
+ uint64_t slice_size;
};
struct radv_cmask_info {
@@ -2081,7 +2082,8 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
const VkImageSubresourceRange *range, uint32_t value);
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
- struct radv_image *image);
+ struct radv_image *image,
+ const VkImageSubresourceRange *range);
struct radv_fence {
struct radeon_winsys_fence *fence;
--
2.22.0
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