[Mesa-dev] [PATCH 4/6] radv: implement clearing DCC layers on GFX8

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
 src/amd/vulkan/radv_meta_clear.c | 6 ++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1f3fdd1abd0..c79543a3246 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4972,7 +4972,8 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
 			if (!surf_level->dcc_fast_clear_size)
 				break;
 
-			size = surf_level->dcc_offset + surf_level->dcc_fast_clear_size;
+			size = surf_level->dcc_offset +
+			       surf_level->dcc_fast_clear_size * image->info.array_size;
 		}
 
 		/* Initialize the mipmap levels without DCC. */
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index e5181daf0f2..f12cf23660a 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1379,6 +1379,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
 	radv_update_dcc_metadata(cmd_buffer, image, range, true);
 
 	for (uint32_t l = 0; l < level_count; l++) {
+		uint32_t dcc_slice_size = image->planes[0].surface.dcc_slice_size;
 		uint64_t offset = image->offset + image->dcc_offset;
 		uint32_t level = range->baseMipLevel + l;
 		uint64_t size;
@@ -1397,8 +1398,9 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
 			 * fast clear path fallbacks to slow clears if one
 			 * level can't be fast cleared.
 			 */
-			offset += surf_level->dcc_offset;
-			size = surf_level->dcc_fast_clear_size;
+			offset += surf_level->dcc_offset +
+				  dcc_slice_size * range->baseArrayLayer;
+			size = surf_level->dcc_fast_clear_size * radv_get_layerCount(image, range);
 		}
 
 		flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
-- 
2.22.0