[Mesa-dev] [PATCH 1/3] radeonsi/nir: call some more var optimisation passes

[Timothy Arceri]

shader-db results (VEGA64):

Totals from affected shaders:
SGPRS: 5328912 -> 5329680 (0.01 %)
VGPRS: 2969308 -> 2969164 (-0.00 %)
Spilled SGPRs: 37921 -> 37917 (-0.01 %)
Spilled VGPRs: 32882 -> 29024 (-11.73 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 1400 -> 1200 (-14.29 %) dwords per thread
Code Size: 121126000 -> 121282784 (0.13 %) bytes
LDS: 1501 -> 1501 (0.00 %) blocks
Max Waves: 933188 -> 933229 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
---
 src/gallium/drivers/radeonsi/si_shader_nir.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 25429fdeab7..5ac18e2ebc8 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -841,9 +841,6 @@ si_lower_nir(struct si_shader_selector* sel)
 	 * - ensure constant offsets for texture instructions are folded
 	 *   and copy-propagated
 	 */
-	NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
-	NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
-	NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
 
 	static const struct nir_lower_tex_options lower_tex_options = {
 		.lower_txp = ~0u,
@@ -866,6 +863,14 @@ si_lower_nir(struct si_shader_selector* sel)
 	do {
 		progress = false;
 
+		NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
+
+		NIR_PASS(progress, sel->nir, nir_opt_copy_prop_vars);
+		NIR_PASS(progress, sel->nir, nir_opt_dead_write_vars);
+
+		NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
+		NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
+
 		/* (Constant) copy propagation is needed for txf with offsets. */
 		NIR_PASS(progress, sel->nir, nir_copy_prop);
 		NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
-- 
2.20.1