[Mesa-dev] [PATCH] radv: do not lower UBO/SSBO access to offsets

[Samuel Pitoiset]

On 3/28/19 10:18 AM, Bas Nieuwenhuizen wrote:
> R-b
>
> Though not sure it really helps given code size increase?
I haven't benchmarked F12017 yet. The code size increases seems to be 
LLVM related but that shouldn't matter much.
>
> On Wed, Mar 27, 2019, 10:13 AM Samuel Pitoiset 
> <samuel.pitoiset at gmail.com <mailto:samuel.pitoiset at gmail.com>> wrote:
>
>     This helps few compute shaders, mostly for F12017.
>
>     27670 shaders in 14347 tests
>     Totals:
>     SGPRS: 1231173 -> 1231173 (0.00 %)
>     VGPRS: 866056 -> 865928 (-0.01 %)
>     Spilled SGPRs: 24201 -> 24201 (0.00 %)
>     Code Size: 46137040 -> 46144868 (0.02 %) bytes
>     Max Waves: 232287 -> 232302 (0.01 %)
>
>     Totals from affected shaders:
>     SGPRS: 24624 -> 24624 (0.00 %)
>     VGPRS: 25960 -> 25832 (-0.49 %)
>     Spilled SGPRs: 0 -> 0 (0.00 %)
>     Code Size: 2922632 -> 2930460 (0.27 %) bytes
>     Max Waves: 1216 -> 1231 (1.23 %)
>
>     Suggested-by: <Jason Ekstrand jason at jlekstrand.net
>     <mailto:jason at jlekstrand.net>>
>     Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com
>     <mailto:samuel.pitoiset at gmail.com>>
>     ---
>      src/amd/common/ac_nir_to_llvm.c | 8 ++++++++
>      src/amd/vulkan/radv_shader.c    | 5 ++++-
>      2 files changed, 12 insertions(+), 1 deletion(-)
>
>     diff --git a/src/amd/common/ac_nir_to_llvm.c
>     b/src/amd/common/ac_nir_to_llvm.c
>     index b25cc6a0a84..c46d98e6dd9 100644
>     --- a/src/amd/common/ac_nir_to_llvm.c
>     +++ b/src/amd/common/ac_nir_to_llvm.c
>     @@ -3275,6 +3275,14 @@ static void visit_intrinsic(struct
>     ac_nir_context *ctx,
>             case nir_intrinsic_vulkan_resource_reindex:
>                     result = visit_vulkan_resource_reindex(ctx, instr);
>                     break;
>     +       case nir_intrinsic_load_vulkan_descriptor: {
>     +               LLVMValueRef values[2] = {
>     +                       get_src(ctx, instr->src[0]),
>     +                       ctx->ac.i32_0,
>     +               };
>     +               result = ac_build_gather_values(&ctx->ac, values, 2);
>     +               break;
>     +       }
>             case nir_intrinsic_store_ssbo:
>                     visit_store_ssbo(ctx, instr);
>                     break;
>     diff --git a/src/amd/vulkan/radv_shader.c
>     b/src/amd/vulkan/radv_shader.c
>     index 19a807df199..2751302e8b9 100644
>     --- a/src/amd/vulkan/radv_shader.c
>     +++ b/src/amd/vulkan/radv_shader.c
>     @@ -220,7 +220,6 @@ radv_shader_compile_to_nir(struct radv_device
>     *device,
>                             }
>                     }
>                     const struct spirv_to_nir_options spirv_options = {
>     -                       .lower_ubo_ssbo_access_to_offsets = true,
>                             .caps = {
>     .descriptor_array_dynamic_indexing = true,
>                                     .device_group = true,
>     @@ -306,6 +305,10 @@ radv_shader_compile_to_nir(struct radv_device
>     *device,
>                     NIR_PASS_V(nir, nir_lower_system_values);
>                     NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
>                     NIR_PASS_V(nir, nir_lower_frexp);
>     +
>     +               NIR_PASS_V(nir, nir_lower_explicit_io,
>     +                         nir_var_mem_ubo | nir_var_mem_ssbo,
>     +  nir_address_format_32bit_index_offset);
>             }
>
>             /* Vulkan uses the separate-shader linking model */
>     -- 
>     2.21.0
>
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