[Mesa-dev] [PATCH 6/6] radeonsi: raise the alignment of LDS memory for compute shaders

[Nicolai Hähnle]

From: Nicolai Hähnle <nicolai.haehnle at amd.com>

This implies that the memory will always be at address 0, which allows
LLVM to generate slightly better code.
---
 src/gallium/drivers/radeonsi/si_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 0cf4d01a36f..91f4c177bd0 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2201,21 +2201,21 @@ void si_declare_compute_memory(struct si_shader_context *ctx)
 
 	LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
 	LLVMValueRef var;
 
 	assert(!ctx->ac.lds);
 
 	var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
 	                                  LLVMArrayType(ctx->i8, lds_size),
 	                                  "compute_lds",
 	                                  AC_ADDR_SPACE_LDS);
-	LLVMSetAlignment(var, 4);
+	LLVMSetAlignment(var, 64 * 1024);
 
 	ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
 }
 
 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
 				    const struct tgsi_full_declaration *decl)
 {
 	assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
 	assert(decl->Range.First == decl->Range.Last);
 
-- 
2.20.1