[Mesa-dev] [PATCH 3/3] r600+radeonsi: use ctx_query_reset_status on radeon
Marek Olšák
maraeo at gmail.com
Fri May 10 05:20:59 UTC 2019
From: Marek Olšák <marek.olsak at amd.com>
This allows a nice cleanup, because the winsys always handles it.
---
src/amd/common/ac_gpu_info.c | 2 --
src/amd/common/ac_gpu_info.h | 1 -
src/gallium/drivers/r600/r600_pipe_common.c | 16 ++---------
src/gallium/drivers/r600/r600_pipe_common.h | 1 -
src/gallium/drivers/radeon/radeon_winsys.h | 1 -
src/gallium/drivers/radeonsi/si_get.c | 3 +--
src/gallium/drivers/radeonsi/si_pipe.c | 27 ++-----------------
src/gallium/drivers/radeonsi/si_pipe.h | 1 -
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 3 ---
.../winsys/radeon/drm/radeon_drm_winsys.c | 5 ----
10 files changed, 5 insertions(+), 55 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index e46424dd885..02c2086f684 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -372,21 +372,20 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_syncobj = has_syncobj(fd);
info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
info->has_local_buffers = info->drm_minor >= 20;
info->kernel_flushes_hdp_before_ib = true;
info->htile_cmask_support_1d_tiling = true;
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->has_bo_metadata = true;
info->has_gpu_reset_status_query = true;
- info->has_gpu_reset_counter_query = false;
info->has_eqaa_surface_allocator = true;
info->has_format_bc1_through_bc7 = true;
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
info->drm_minor >= 2;
info->has_indirect_compute_dispatch = true;
/* SI doesn't support unaligned loads. */
info->has_unaligned_shader_loads = info->chip_class != SI;
/* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
* these faults are mitigated in software.
@@ -556,21 +555,20 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_syncobj = %u\n", info->has_syncobj);
printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
printf(" has_local_buffers = %u\n", info->has_local_buffers);
printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
- printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
printf("Shader core info:\n");
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 946c2df82d0..25bd33c1afa 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -103,21 +103,20 @@ struct radeon_info {
bool has_syncobj;
bool has_syncobj_wait_for_submit;
bool has_fence_to_handle;
bool has_ctx_priority;
bool has_local_buffers;
bool kernel_flushes_hdp_before_ib;
bool htile_cmask_support_1d_tiling;
bool si_TA_CS_BC_BASE_ADDR_allowed;
bool has_bo_metadata;
bool has_gpu_reset_status_query;
- bool has_gpu_reset_counter_query;
bool has_eqaa_surface_allocator;
bool has_format_bc1_through_bc7;
bool kernel_flushes_tc_l2_after_ib;
bool has_indirect_compute_dispatch;
bool has_unaligned_shader_loads;
bool has_sparse_vm_mappings;
bool has_2d_tiling;
bool has_read_registers_query;
/* Shader cores. */
diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c
index bce45ea0456..b39b99e6fcb 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.c
+++ b/src/gallium/drivers/r600/r600_pipe_common.c
@@ -539,28 +539,22 @@ void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
{
FREE(saved->ib);
FREE(saved->bo_list);
memset(saved, 0, sizeof(*saved));
}
static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
- unsigned latest = rctx->ws->query_value(rctx->ws,
- RADEON_GPU_RESET_COUNTER);
- if (rctx->gpu_reset_counter == latest)
- return PIPE_NO_RESET;
-
- rctx->gpu_reset_counter = latest;
- return PIPE_UNKNOWN_CONTEXT_RESET;
+ return rctx->ws->ctx_query_reset_status(rctx->ctx);
}
static void r600_set_debug_callback(struct pipe_context *ctx,
const struct pipe_debug_callback *cb)
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
if (cb)
rctx->debug = *cb;
else
@@ -666,27 +660,21 @@ bool r600_common_context_init(struct r600_common_context *rctx,
/* evergreen_compute.c has a special codepath for global buffers.
* Everything else can use the direct path.
*/
if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
(context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
rctx->b.buffer_subdata = u_default_buffer_subdata;
else
rctx->b.buffer_subdata = r600_buffer_subdata;
- if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
- rctx->b.get_device_reset_status = r600_get_reset_status;
- rctx->gpu_reset_counter =
- rctx->ws->query_value(rctx->ws,
- RADEON_GPU_RESET_COUNTER);
- }
-
+ rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
r600_init_context_texture_functions(rctx);
r600_init_viewport_functions(rctx);
r600_streamout_init(rctx);
r600_query_init(rctx);
cayman_init_msaa(&rctx->b);
rctx->allocator_zeroed_memory =
u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
diff --git a/src/gallium/drivers/r600/r600_pipe_common.h b/src/gallium/drivers/r600/r600_pipe_common.h
index c4e60e9db89..b43b7eecd10 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.h
+++ b/src/gallium/drivers/r600/r600_pipe_common.h
@@ -510,21 +510,20 @@ struct r600_common_context {
struct radeon_winsys_ctx *ctx;
enum radeon_family family;
enum chip_class chip_class;
struct r600_ring gfx;
struct r600_ring dma;
struct pipe_fence_handle *last_gfx_fence;
struct pipe_fence_handle *last_sdma_fence;
struct r600_resource *eop_bug_scratch;
unsigned num_gfx_cs_flushes;
unsigned initial_gfx_cs_size;
- unsigned gpu_reset_counter;
unsigned last_dirty_tex_counter;
unsigned last_compressed_colortex_counter;
unsigned last_num_draw_calls;
struct threaded_context *tc;
struct u_suballocator *allocator_zeroed_memory;
struct slab_child_pool pool_transfers;
struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
/* Current unaccounted memory usage. */
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 0c71b59ae04..3def92b552c 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -116,21 +116,20 @@ enum radeon_value_id {
RADEON_GFX_IB_SIZE_COUNTER,
RADEON_NUM_BYTES_MOVED,
RADEON_NUM_EVICTIONS,
RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
RADEON_VRAM_USAGE,
RADEON_VRAM_VIS_USAGE,
RADEON_GTT_USAGE,
RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
RADEON_CURRENT_SCLK,
RADEON_CURRENT_MCLK,
- RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
RADEON_CS_THREAD_TIME,
};
enum radeon_bo_priority {
/* Each group of two has the same priority. */
RADEON_PRIO_FENCE = 0,
RADEON_PRIO_TRACE,
RADEON_PRIO_SO_FILLED_SIZE = 2,
RADEON_PRIO_QUERY,
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 700777186d8..22abcaee563 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -155,22 +155,21 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
case PIPE_CAP_IMAGE_LOAD_FORMATTED:
case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- return sscreen->info.has_gpu_reset_status_query ||
- sscreen->info.has_gpu_reset_counter_query;
+ return sscreen->info.has_gpu_reset_status_query;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
return sscreen->info.has_2d_tiling;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return SI_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 4d36fd46a9b..aa7f012f071 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -270,35 +270,21 @@ static void si_destroy_context(struct pipe_context *context)
util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
si_unref_sdma_uploads(sctx);
FREE(sctx);
}
static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
{
struct si_context *sctx = (struct si_context *)ctx;
- if (sctx->screen->info.has_gpu_reset_status_query)
- return sctx->ws->ctx_query_reset_status(sctx->ctx);
-
- if (sctx->screen->info.has_gpu_reset_counter_query) {
- unsigned latest = sctx->ws->query_value(sctx->ws,
- RADEON_GPU_RESET_COUNTER);
-
- if (sctx->gpu_reset_counter == latest)
- return PIPE_NO_RESET;
-
- sctx->gpu_reset_counter = latest;
- return PIPE_UNKNOWN_CONTEXT_RESET;
- }
-
- return PIPE_NO_RESET;
+ return sctx->ws->ctx_query_reset_status(sctx->ctx);
}
static void si_set_device_reset_callback(struct pipe_context *ctx,
const struct pipe_device_reset_callback *cb)
{
struct si_context *sctx = (struct si_context *)ctx;
if (cb)
sctx->device_reset_callback = *cb;
else
@@ -306,24 +292,21 @@ static void si_set_device_reset_callback(struct pipe_context *ctx,
sizeof(sctx->device_reset_callback));
}
bool si_check_device_reset(struct si_context *sctx)
{
enum pipe_reset_status status;
if (!sctx->device_reset_callback.reset)
return false;
- if (!sctx->b.get_device_reset_status)
- return false;
-
- status = sctx->b.get_device_reset_status(&sctx->b);
+ status = sctx->ws->ctx_query_reset_status(sctx->ctx);
if (status == PIPE_NO_RESET)
return false;
sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
return true;
}
/* Apitrace profiling:
* 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
* 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
@@ -406,26 +389,20 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
sctx->ws = sscreen->ws;
sctx->family = sscreen->info.family;
sctx->chip_class = sscreen->info.chip_class;
- if (sscreen->info.has_gpu_reset_counter_query) {
- sctx->gpu_reset_counter =
- sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
- }
-
-
if (sctx->chip_class == CIK ||
sctx->chip_class == VI ||
sctx->chip_class == GFX9) {
sctx->eop_bug_scratch = si_resource(
pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
16 * sscreen->info.num_render_backends));
if (!sctx->eop_bug_scratch)
goto fail;
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 949fa0755cb..4061bf139fb 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -844,21 +844,20 @@ struct si_context {
unsigned wait_mem_number;
uint16_t prefetch_L2_mask;
bool has_graphics;
bool gfx_flush_in_progress:1;
bool gfx_last_ib_is_busy:1;
bool compute_is_busy:1;
unsigned num_gfx_cs_flushes;
unsigned initial_gfx_cs_size;
- unsigned gpu_reset_counter;
unsigned last_dirty_tex_counter;
unsigned last_dirty_buf_counter;
unsigned last_compressed_colortex_counter;
unsigned last_num_draw_calls;
unsigned flags; /* flush flags */
/* Current unaccounted memory usage. */
uint64_t vram;
uint64_t gtt;
/* Atoms (direct states). */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index e847c5cff10..cf02311864e 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -212,23 +212,20 @@ static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
return heap.heap_usage;
case RADEON_GPU_TEMPERATURE:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
return retval;
case RADEON_CURRENT_SCLK:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
return retval;
case RADEON_CURRENT_MCLK:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
return retval;
- case RADEON_GPU_RESET_COUNTER:
- assert(0);
- return 0;
case RADEON_CS_THREAD_TIME:
return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
}
return 0;
}
static bool amdgpu_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3f0eb1772e9..de20edbe662 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -566,21 +566,20 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_start_alignment = 4096;
ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
ws->info.drm_minor >= 38;
ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->info.has_bo_metadata = false;
ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
- ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
ws->info.kernel_flushes_tc_l2_after_ib = true;
/* Old kernels disallowed register writes via COPY_DATA
* that are used for indirect compute dispatches. */
ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
(ws->info.chip_class == SI &&
ws->info.drm_minor >= 45);
/* SI doesn't support unaligned loads. */
ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
@@ -723,24 +722,20 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
"gpu-temp", (uint32_t*)&retval);
return retval;
case RADEON_CURRENT_SCLK:
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
"current-gpu-sclk", (uint32_t*)&retval);
return retval;
case RADEON_CURRENT_MCLK:
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
"current-gpu-mclk", (uint32_t*)&retval);
return retval;
- case RADEON_GPU_RESET_COUNTER:
- radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
- "gpu-reset-counter", (uint32_t*)&retval);
- return retval;
case RADEON_CS_THREAD_TIME:
return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
}
return 0;
}
static bool radeon_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
--
2.17.1
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