[Mesa-dev] [PATCH 2/3] winsys/radeon: implement ctx_query_reset_status by copying radeonsi
Marek Olšák
maraeo at gmail.com
Fri May 10 05:20:58 UTC 2019
From: Marek Olšák <marek.olsak at amd.com>
To make it behave like amdgpu. I'm just trying to move this out of
radeonsi. The radeonsi code will be removed in the next commit.
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 29 +++++++++++++++----
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 5 ++++
.../winsys/radeon/drm/radeon_drm_winsys.c | 14 ++++++++-
.../winsys/radeon/drm/radeon_drm_winsys.h | 1 +
4 files changed, 43 insertions(+), 6 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 490c246d6e0..02c10f7ea7d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -66,28 +66,46 @@
#define RELOC_DWORDS (sizeof(struct drm_radeon_cs_reloc) / sizeof(uint32_t))
static struct pipe_fence_handle *
radeon_cs_create_fence(struct radeon_cmdbuf *rcs);
static void radeon_fence_reference(struct pipe_fence_handle **dst,
struct pipe_fence_handle *src);
static struct radeon_winsys_ctx *radeon_drm_ctx_create(struct radeon_winsys *ws)
{
- /* No context support here. Just return the winsys pointer
- * as the "context". */
- return (struct radeon_winsys_ctx*)ws;
+ struct radeon_ctx *ctx = CALLOC_STRUCT(radeon_ctx);
+ if (!ctx)
+ return NULL;
+
+ ctx->ws = (struct radeon_drm_winsys*)ws;
+ ctx->gpu_reset_counter = radeon_drm_get_gpu_reset_counter(ctx->ws);
+ return (struct radeon_winsys_ctx*)ctx;
}
static void radeon_drm_ctx_destroy(struct radeon_winsys_ctx *ctx)
{
- /* No context support here. */
+ FREE(ctx);
+}
+
+static enum pipe_reset_status
+radeon_drm_ctx_query_reset_status(struct radeon_winsys_ctx *rctx)
+{
+ struct radeon_ctx *ctx = (struct radeon_ctx*)rctx;
+
+ unsigned latest = radeon_drm_get_gpu_reset_counter(ctx->ws);
+
+ if (ctx->gpu_reset_counter == latest)
+ return PIPE_NO_RESET;
+
+ ctx->gpu_reset_counter = latest;
+ return PIPE_UNKNOWN_CONTEXT_RESET;
}
static bool radeon_init_cs_context(struct radeon_cs_context *csc,
struct radeon_drm_winsys *ws)
{
int i;
csc->fd = ws->fd;
csc->chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
@@ -146,21 +164,21 @@ static void radeon_destroy_cs_context(struct radeon_cs_context *csc)
static struct radeon_cmdbuf *
radeon_drm_cs_create(struct radeon_winsys_ctx *ctx,
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
struct pipe_fence_handle **fence),
void *flush_ctx,
bool stop_exec_on_failure)
{
- struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)ctx;
+ struct radeon_drm_winsys *ws = ((struct radeon_ctx*)ctx)->ws;
struct radeon_drm_cs *cs;
cs = CALLOC_STRUCT(radeon_drm_cs);
if (!cs) {
return NULL;
}
util_queue_fence_init(&cs->flush_completed);
cs->ws = ws;
cs->flush_cs = flush;
@@ -811,20 +829,21 @@ radeon_drm_cs_add_fence_dependency(struct radeon_cmdbuf *cs,
*
* We currently assume that this does not happen because we don't support
* asynchronous flushes on Radeon.
*/
}
void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
{
ws->base.ctx_create = radeon_drm_ctx_create;
ws->base.ctx_destroy = radeon_drm_ctx_destroy;
+ ws->base.ctx_query_reset_status = radeon_drm_ctx_query_reset_status;
ws->base.cs_create = radeon_drm_cs_create;
ws->base.cs_destroy = radeon_drm_cs_destroy;
ws->base.cs_add_buffer = radeon_drm_cs_add_buffer;
ws->base.cs_lookup_buffer = radeon_drm_cs_lookup_buffer;
ws->base.cs_validate = radeon_drm_cs_validate;
ws->base.cs_check_space = radeon_drm_cs_check_space;
ws->base.cs_get_buffer_list = radeon_drm_cs_get_buffer_list;
ws->base.cs_flush = radeon_drm_cs_flush;
ws->base.cs_get_next_fence = radeon_drm_cs_get_next_fence;
ws->base.cs_is_buffer_referenced = radeon_bo_is_referenced;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index f4c6cbe1fa7..4fa007afa00 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -22,20 +22,25 @@
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#ifndef RADEON_DRM_CS_H
#define RADEON_DRM_CS_H
#include "radeon_drm_bo.h"
+struct radeon_ctx {
+ struct radeon_drm_winsys *ws;
+ uint32_t gpu_reset_counter;
+};
+
struct radeon_bo_item {
struct radeon_bo *bo;
union {
struct {
uint32_t priority_usage;
} real;
struct {
unsigned real_idx;
} slab;
} u;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 293372cc26d..3f0eb1772e9 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -565,21 +565,21 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
(ws->info.family == CHIP_HAWAII &&
ws->accel_working2 < 3);
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_start_alignment = 4096;
ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
ws->info.drm_minor >= 38;
ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->info.has_bo_metadata = false;
- ws->info.has_gpu_reset_status_query = false;
+ ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
ws->info.kernel_flushes_tc_l2_after_ib = true;
/* Old kernels disallowed register writes via COPY_DATA
* that are used for indirect compute dispatches. */
ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
(ws->info.chip_class == SI &&
ws->info.drm_minor >= 45);
/* SI doesn't support unaligned loads. */
@@ -649,20 +649,32 @@ static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
case RADEON_FID_R300_CMASK_ACCESS:
return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
&cs->ws->cmask_owner_mutex,
RADEON_INFO_WANT_CMASK, "AA optimizations",
enable);
}
return false;
}
+uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws)
+{
+ uint64_t retval = 0;
+
+ if (!ws->info.has_gpu_reset_status_query)
+ return 0;
+
+ radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
+ "gpu-reset-counter", (uint32_t*)&retval);
+ return retval;
+}
+
static uint64_t radeon_query_value(struct radeon_winsys *rws,
enum radeon_value_id value)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
uint64_t retval = 0;
switch (value) {
case RADEON_REQUESTED_VRAM_MEMORY:
return ws->allocated_vram;
case RADEON_REQUESTED_GTT_MEMORY:
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
index 03d96ea4c10..3ebe1d7708c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
@@ -102,13 +102,14 @@ struct radeon_drm_winsys {
/* multithreaded command submission */
struct util_queue cs_queue;
};
static inline struct radeon_drm_winsys *
radeon_drm_winsys(struct radeon_winsys *base)
{
return (struct radeon_drm_winsys*)base;
}
+uint32_t radeon_drm_get_gpu_reset_counter(struct radeon_drm_winsys *ws);
void radeon_surface_init_functions(struct radeon_drm_winsys *ws);
#endif
--
2.17.1
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