[Mesa-stable] [PATCH 1/2] [v3] i965/skl: Add GT4 PCI IDs

[Ian Romanick]

On 10/29/2015 05:30 PM, Ben Widawsky wrote:
> Like other gen8+ hardware, the hardware automatically scales up thread counts
> and URB sizes, so there is no need to do anything but add the PCI IDs.

Give the v3 change, is that really true?

> FINISHME: This patch still needs testing before merge.
> 
> v2: Remove the PCI ID removal. That should be done as part of the next patch.
> 
> v3: Update the wm thread count to support GT4.
> 
> Cc: mesa-stable at lists.freedesktop.org
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
>  include/pci_ids/i965_pci_ids.h              | 4 ++++
>  src/mesa/drivers/dri/i965/brw_device_info.c | 6 +++++-
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
> index 8a42599..626064a 100644
> --- a/include/pci_ids/i965_pci_ids.h
> +++ b/include/pci_ids/i965_pci_ids.h
> @@ -124,6 +124,10 @@ CHIPSET(0x1921, skl_gt2, "Intel(R) Skylake ULT GT2F")
>  CHIPSET(0x1926, skl_gt3, "Intel(R) Skylake ULT GT3")
>  CHIPSET(0x192A, skl_gt3, "Intel(R) Skylake SRV GT3")
>  CHIPSET(0x192B, skl_gt3, "Intel(R) Skylake Halo GT3")
> +CHIPSET(0x1932, skl_gt4, "Intel(R) Skylake GT4")
> +CHIPSET(0x193A, skl_gt4, "Intel(R) Skylake GT4")
> +CHIPSET(0x193B, skl_gt4, "Intel(R) Skylake GT4")
> +CHIPSET(0x193D, skl_gt4, "Intel(R) Skylake GT4")
>  CHIPSET(0x22B0, chv,     "Intel(R) HD Graphics (Cherryview)")
>  CHIPSET(0x22B1, chv,     "Intel(R) HD Graphics (Cherryview)")
>  CHIPSET(0x22B2, chv,     "Intel(R) HD Graphics (Cherryview)")
> diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
> index e86b530..2ebc084 100644
> --- a/src/mesa/drivers/dri/i965/brw_device_info.c
> +++ b/src/mesa/drivers/dri/i965/brw_device_info.c
> @@ -311,7 +311,7 @@ static const struct brw_device_info brw_device_info_chv = {
>     .max_gs_threads = 336,                           \
>     .max_hs_threads = 336,                           \
>     .max_ds_threads = 336,                           \
> -   .max_wm_threads = 64 * 6,                        \
> +   .max_wm_threads = 64 * 9,                        \
>     .max_cs_threads = 56,                            \
>     .urb = {                                         \
>        .size = 384,                                  \
> @@ -335,6 +335,10 @@ static const struct brw_device_info brw_device_info_skl_gt3 = {
>     GEN9_FEATURES, .gt = 3,
>  };
>  
> +static const struct brw_device_info brw_device_info_skl_gt4 = {
> +   GEN9_FEATURES, .gt = 4,
> +};
> +
>  static const struct brw_device_info brw_device_info_bxt = {
>     GEN9_FEATURES,
>     .is_broxton = 1,
>