[Nouveau] Interrupt setting

[Luca Barbieri]

> So a GPU itself updates the sequence # of each fence in a specific register, and we can let the Nouveau driver wait for a target
> value to be written.
> Do you know when the value is actually written?

When the FIFO command instructing the GPU to do the write is executed.

> If it is written when a "DMA transfer" is done, we dont know exactly when the corresponding GPU operation is finished.
> Do you think it is possible to wait for a completion of a "GPU operation"?

The current assumption is that FIFO commands are executed
synchronously, so when the FIFO executes the command to update the
fence value, all previous FIFO commands should have been completed.

The current driver just does a CPU busy loop, continuously reading the
fence register until the value read is large enough.

There should be some work by Francisco Jerez and perhaps Ben Skeggs on
using an interrupt-based mechanism instead (the one you described,
most likely), but I'm not sure what the status of that is.