[Nouveau] GSOC project

[Karol Herbst]

Hi,

I think a nice project would be to write an application to figure out those latencies automatically maybe even based on envydis.

It could generate latency information based on thread count, register usage, instruction/instruction class, hw unit used. Or even tries to figure out what kind of units exist. Like instructions out of a group which are free to issue/execute after instructions out of another one.

I could imagine, that this allone might be a really huge project, but useful for future and past chipsets.

On 17 January 2017 10:28:20 p.m. GMT+01:00, Ilia Mirkin <imirkin at alum.mit.edu> wrote:
>There's not a lot of information about it. Basically we need 2
>instruction
>scheduling passes -- one pre-RA and one post-RA. The prerequisites are
>"know how compilers work" and "have a GPU that you can test performance
>on".
>
>I won't beat around the bush - this is a very tough project. Every
>attempt
>at it so far has basically failed. There are a lot of issues that have
>to
>be dealt with, like how to properly get the instruction latency
>information, and how to apply it while taking ideas like register
>pressure
>into account.
>
>You can read up on the nouveau codegen compiler here:
>https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/codegen/
>
>Cheers,
>
>  -ilia
>
>
>On Tue, Jan 17, 2017 at 8:58 AM, Shailesh Tripathi <
>shailesh.tripathi.ece13 at itbhu.ac.in> wrote:
>
>> Hello,
>> I am quite interested in the project "Instruction Scheduler" under
>X.org.
>> Please tell me where can I find a detailed idea of the project and
>how to
>> start it. I think I have the given prerequisites.
>>
>> Regards
>> Shailesh Tripathi
>>
>>
>> Shailesh Tripathi
>> B.Tech. Part-IV
>> Electronics Engineering
>> IIT-BHU (Varanasi)
>>
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