[Openchrome-devel] VX800 and interlaced mode

[Anders Gunnarsson]

On m?n, 2009-03-02 at 18:14 +0100, Anders Gunnarsson wrote:
> Den Sunday 01 March 2009 22:29:06 skrev Xavier Bachelot:
> > Anders Gunnarsson wrote:
> > > Bump
> > >
> > > Anyone?
> > >
> > > Sunday 15 February 2009 18:47:10 you wrote:
> > >> Hi all,
> > >>
> > >> I try to get my vx800 based M700 into interlaced mode. The
> response I
> > >> get from the driver is "interlace mode not supported". Is this a
> > >> hardware limitation or is it a limitation from the driver?
> > >>
> > >> If it is the driver, can someone point me in the right direction
> for a
> > >> solution.
> > >>
> > >> My driver is openchrome-svn checked out like 2 months ago, if
> something
> > >> has changed lately.
> > >>
> > >> Best regards
> > >> /Anders
> >
> > The best I can do is a link to the VX800 doc. I have no idea if
> > interlaced mode is supported or not, but iirc, it was not supported
> on
> > the earlier chipsets.
> >
> > http://www.openchrome.org/trac/wiki/Development#a2D
> >
> > Regards,
> > Xavier
> 
> Thanks!
> 
> Hadn't seen that documentation earlier. Only the one at via's linux
> site.
> 
> IO Port / Index: 3X5.33 HSynch Adjuster, bit 6 Primary Display
> Interlace Mode seem suspicious. I'll see if I can manage to make
> something out of this information myself or not. All help is
> appreciated.
> 
> /Anders
> 

I finally got some time over to have a look at this again. Tried to do
the changes below without much luck. This means I get no image on my tv
over my non verified vga-scart cable. Could someone help me to verify if
the result is an interlaced signal?

I don't know if I got things right, since I'm not much of a c developer
and not at all an xorg developer. The manual states that interlace mode
on primary display is set through 3X5.33 (port 3B5, index 33?) bit 6
which is what I tried to do. Then I don't know if this is sufficient or
if there are more things that need to be done like manipulating nuber of
rows etc. From what I found on interlace in the manual there is a
similar setting for secondary display, and some IGA2 Interlace Half Line
Register on 3X5.AB-AC.

Any help is appreciated
/Anders

----
Index: src/via_crtc.c
===================================================================
--- src/via_crtc.c	(revision 758)
+++ src/via_crtc.c	(working copy)
@@ -184,6 +184,11 @@
     }
 
     /* Crtc registers */
+    /* Interlace */
+    if (mode->Flags & V_INTERLACE) {
+        ViaCrtcMask(hwp, 0x33, 0x40, 0xFF);
+    }
+
     /* horizontal total : 4100 */
     temp = (mode->CrtcHTotal >> 3) - 5;
     hwp->writeCrtc(hwp, 0x00, temp & 0xFF);
Index: src/via_mode.c
===================================================================
--- src/via_mode.c	(revision 758)
+++ src/via_mode.c	(working copy)
@@ -882,8 +882,14 @@
     DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "ViaValidMode: Validating %s (%
d)\n",
                      mode->name, mode->Clock));
 
-    if (mode->Flags & V_INTERLACE)
-        return MODE_NO_INTERLACE;
+    if (mode->Flags & V_INTERLACE) {
+        switch (pVia->Chipset) {
+            case VIA_VX800:
+                break;
+            default:
+                return MODE_NO_INTERLACE;
+        }
+    }
 
     if (pVia->UseLegacyModeSwitch) {