[Openchrome-devel] drm-openchrome: Branch 'drm-next-3.19' - 4 commits - drivers/gpu/drm
Kevin Brace
kevinbrace at kemper.freedesktop.org
Thu Dec 21 02:47:02 UTC 2017
drivers/gpu/drm/openchrome/via_crtc.c | 60 ++++++++++++++++++++--------------
drivers/gpu/drm/openchrome/via_drv.h | 4 +-
2 files changed, 38 insertions(+), 26 deletions(-)
New commits:
commit 2a1cceb959dbec77e940a3588172a938f8c04cdb
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Wed Dec 20 20:46:22 2017 -0600
drm/openchrome: Version bumped to 3.0.67
Display FIFO fixes for P4M800 Pro chipset. Another small adjustment
(PREQ / TREQ control bit) for UniChrome and UniChrome Pro devices.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_drv.h b/drivers/gpu/drm/openchrome/via_drv.h
index 687ff7c57af9..db2e32936325 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -30,11 +30,11 @@
#define DRIVER_AUTHOR "OpenChrome Project"
#define DRIVER_NAME "openchrome"
#define DRIVER_DESC "OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE "20171219"
+#define DRIVER_DATE "20171220"
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 66
+#define DRIVER_PATCHLEVEL 67
#include <linux/module.h>
commit 1f4fd28b66cb2db0ef0b4c6373a485279e14abf5
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Wed Dec 20 20:42:54 2017 -0600
drm/openchrome: Changing P4M800 Pro IGA1 and IGA2 display FIFO parameters
The display FIFO parameters came from VIA Technologies Chrome IGP open
source DDX device driver. IGA2 parameters were copied from IGA1.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index f575c305f640..6ec41dbabec6 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -696,12 +696,18 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
break;
case PCI_DEVICE_ID_VIA_CN700:
- iga->display_queue_expire_num = 0;
- iga->fifo_high_threshold = 64;
- iga->fifo_threshold = 80;
- iga->fifo_max_depth = 96;
- break;
+ /* SR17[7:0] */
+ iga->fifo_max_depth = 128;
+
+ /* SR16[7], SR16[5:0] */
+ iga->fifo_threshold = 32;
+ /* SR18[7], SR18[5:0] */
+ iga->fifo_high_threshold = 56;
+
+ /* SR22[4:0] */
+ iga->display_queue_expire_num = 124;
+ break;
/* CX700 */
case PCI_DEVICE_ID_VIA_VT3157:
iga->fifo_high_threshold = iga->fifo_threshold = 128;
@@ -787,12 +793,6 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
}
}
- /* If resolution > 1280x1024, expire length = 64, else
- expire length = 128 */
- if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CN700) &&
- ((mode->hdisplay > 1280) && (mode->vdisplay > 1024)))
- iga->display_queue_expire_num = 16;
-
/* Set IGA1 Display FIFO Depth Select */
reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
@@ -957,12 +957,18 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
break;
case PCI_DEVICE_ID_VIA_CN700:
- iga->display_queue_expire_num = 128;
- iga->fifo_high_threshold = 32;
- iga->fifo_threshold = 80;
- iga->fifo_max_depth = 96;
- break;
+ /* CR95[7], CR94[7], CR68[7:4] */
+ iga->fifo_max_depth = 128;
+
+ /* CR95[6:4], CR68[3:0] */
+ iga->fifo_threshold = 32;
+ /* CR95[2:0], CR92[3:0] */
+ iga->fifo_high_threshold = 56;
+
+ /* CR94[6:0] */
+ iga->display_queue_expire_num = 124;
+ break;
/* CX700 */
case PCI_DEVICE_ID_VIA_VT3157:
iga->display_queue_expire_num = 128;
@@ -1042,12 +1048,6 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
reg_value = iga->fifo_threshold / 4;
load_value_to_registers(VGABASE, &iga->threshold, reg_value);
} else {
- /* If resolution > 1280x1024, expire length = 64, else
- expire length = 128 */
- if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CN700) &&
- (mode->hdisplay > 1280) && (mode->vdisplay > 1024))
- iga->display_queue_expire_num = 16;
-
/* Set IGA2 Display FIFO Depth Select */
reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
commit 2a574d3a7aa5e7fa09063c819482e701ab1b5173
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Wed Dec 20 20:25:57 2017 -0600
drm/openchrome: Add missing SR22 comments for IGA1
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index 3bc49b89494b..f575c305f640 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -667,8 +667,10 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
if ((fb->bits_per_pixel == 32) &&
(mode->hdisplay >= 1400)) {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 64;
} else {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 128;
}
@@ -685,8 +687,10 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
if ((fb->bits_per_pixel == 32) &&
(mode->hdisplay >= 1400)) {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 64;
} else {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 124;
}
commit 4bd3d8a55b0e8c3902c9d72dc833ff3c84c90055
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Wed Dec 20 19:52:25 2017 -0600
drm/openchrome: Actively Set PREQ / TREQ control bit for IGA1
Apparently, this bit is set for many older devices.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index b3facc4c1aa6..3bc49b89494b 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -747,10 +747,18 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
}
if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
- (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
- /* Force PREQ to be always higer than TREQ. */
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_PM800) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_CN700)) {
+ /* Force PREQ to be always higher than TREQ. */
svga_wseq_mask(VGABASE, 0x18, BIT(6), BIT(6));
+ } else {
+ svga_wseq_mask(VGABASE, 0x18, 0x00, BIT(6));
+ }
+ if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
if (enable_extended_display_fifo) {
reg_value = VIA_READ(0x0298);
VIA_WRITE(0x0298, reg_value | 0x20000000);
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