[Openchrome-devel] drm-openchrome: Branch 'drm-next-4.15' - 2 commits - drivers/gpu/drm
Kevin Brace
kevinbrace at kemper.freedesktop.org
Sun Jan 28 20:56:56 UTC 2018
drivers/gpu/drm/openchrome/via_crtc.c | 81 ++++++++++++++++++++--------------
drivers/gpu/drm/openchrome/via_drv.h | 2
2 files changed, 50 insertions(+), 33 deletions(-)
New commits:
commit d889e07e0d5922fa9f396e7e81af38f080b1ce6c
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jan 28 12:55:22 2018 -0800
drm/openchrome: Version bumped to 3.0.64
More fixes for CLE266 and KM400 chipsets.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_drv.h b/drivers/gpu/drm/openchrome/via_drv.h
index df658fd986f4..6079d7f2d5ac 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -34,7 +34,7 @@
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 63
+#define DRIVER_PATCHLEVEL 64
#include <linux/module.h>
commit 7a7d39fd5b0556cd3676f1b636fd0c530c725c4c
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jan 28 12:52:28 2018 -0800
drm/openchrome: Simplify extended display FIFO control code
This is for CLE266 and KM400 chipsets.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index c6491f472234..75688285e388 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -496,6 +496,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
struct drm_framebuffer *fb)
{
u32 reg_value;
+ bool enable_extended_display_fifo = false;
DRM_DEBUG_KMS("Entered %s.\n", __func__);
@@ -511,6 +512,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
/* SR18[5:0] */
iga->fifo_high_threshold = 92;
+
+ enable_extended_display_fifo = true;
} else {
/* SR17[6:0] */
iga->fifo_max_depth = 128;
@@ -520,6 +523,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
/* SR18[5:0] */
iga->fifo_high_threshold = 56;
+
+ enable_extended_display_fifo = false;
}
if (dev_priv->vram_type <= VIA_MEM_DDR_200) {
@@ -574,6 +579,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
/* SR18[5:0] */
iga->fifo_high_threshold = 92;
+
+ enable_extended_display_fifo = false;
} else {
/* SR17[6:0] */
iga->fifo_max_depth = 128;
@@ -583,6 +590,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
/* SR18[5:0] */
iga->fifo_high_threshold = 56;
+
+ enable_extended_display_fifo = false;
}
if (dev_priv->vram_type <= VIA_MEM_DDR_200) {
@@ -612,6 +621,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
}
}
break;
+
case PCI_DEVICE_ID_VIA_KM400:
if ((mode->hdisplay >= 1600) &&
(dev_priv->vram_type <= VIA_MEM_DDR_200)) {
@@ -634,6 +644,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
iga->fifo_high_threshold = 92;
}
+ enable_extended_display_fifo = false;
+
if (dev_priv->vram_type <= VIA_MEM_DDR_200) {
if (mode->hdisplay >= 1600) {
/* SR22[4:0] */
@@ -726,20 +738,29 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
(dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
/* Force PREQ to be always higer than TREQ. */
svga_wseq_mask(VGABASE, 0x18, BIT(6), BIT(6));
- }
- if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
- (dev_priv->revision == CLE266_REVISION_AX) &&
- (mode->hdisplay > 1024)) {
- reg_value = VIA_READ(0x0298);
- VIA_WRITE(0x0298, reg_value | 0x20000000);
+ if (enable_extended_display_fifo) {
+ reg_value = VIA_READ(0x0298);
+ VIA_WRITE(0x0298, reg_value | 0x20000000);
- /* Turn on IGA1 extended display FIFO. */
- reg_value = VIA_READ(0x0230);
- VIA_WRITE(0x0230, reg_value | 0x00200000);
+ /* Turn on IGA1 extended display FIFO. */
+ reg_value = VIA_READ(0x0230);
+ VIA_WRITE(0x0230, reg_value | 0x00200000);
- reg_value = VIA_READ(0x0298);
- VIA_WRITE(0x0298, reg_value & (~0x20000000));
+ reg_value = VIA_READ(0x0298);
+ VIA_WRITE(0x0298, reg_value & (~0x20000000));
+ } else {
+ reg_value = VIA_READ(0x0298);
+ VIA_WRITE(0x0298, reg_value | 0x20000000);
+
+ /* Turn off IGA1 extended display FIFO. */
+ reg_value = VIA_READ(0x0230);
+ VIA_WRITE(0x0230, reg_value & (~0x00200000));
+
+ reg_value = VIA_READ(0x0298);
+ VIA_WRITE(0x0298, reg_value & (~0x20000000));
+
+ }
}
/* If resolution > 1280x1024, expire length = 64, else
@@ -775,6 +796,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
struct drm_framebuffer *fb)
{
u32 reg_value;
+ bool enable_extended_display_fifo = false;
DRM_DEBUG_KMS("Entered %s.\n", __func__);
@@ -792,12 +814,16 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
/* CR68[3:0] */
iga->fifo_threshold = 44;
+
+ enable_extended_display_fifo = true;
} else {
/* CR68[7:4] */
iga->fifo_max_depth = 56;
/* CR68[3:0] */
iga->fifo_threshold = 28;
+
+ enable_extended_display_fifo = false;
}
/* dev_priv->revision == CLE266_REVISION_CX */
} else {
@@ -807,12 +833,16 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
/* CR68[3:0] */
iga->fifo_threshold = 44;
+
+ enable_extended_display_fifo = false;
} else {
/* CR68[7:4] */
iga->fifo_max_depth = 56;
/* CR68[3:0] */
iga->fifo_threshold = 28;
+
+ enable_extended_display_fifo = false;
}
}
@@ -825,8 +855,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
/* CR68[3:0] */
iga->fifo_threshold = 44;
- /* Enable IGA2 extended display FIFO. */
- svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+ enable_extended_display_fifo = true;
} else if (((mode->hdisplay > 1024) &&
(fb->format->depth == 32) &&
(dev_priv->vram_type <= VIA_MEM_DDR_333))
@@ -839,8 +868,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
/* CR68[3:0] */
iga->fifo_threshold = 28;
- /* Enable IGA2 extended display FIFO. */
- svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+ enable_extended_display_fifo = true;
} else if (((mode->hdisplay > 1280) &&
(fb->format->depth == 16) &&
(dev_priv->vram_type <= VIA_MEM_DDR_333))
@@ -853,8 +881,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
/* CR68[3:0] */
iga->fifo_threshold = 44;
- /* Enable IGA2 extended display FIFO. */
- svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+ enable_extended_display_fifo = true;
} else {
/* CR68[7:4] */
iga->fifo_max_depth = 56;
@@ -862,8 +889,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
/* CR68[3:0] */
iga->fifo_threshold = 28;
- /* Disable IGA2 extended display FIFO. */
- svga_wcrt_mask(VGABASE, 0x6a, 0x00, BIT(5));
+ enable_extended_display_fifo = false;
}
break;
@@ -948,26 +974,17 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
(dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
- if (((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
- (dev_priv->revision == CLE266_REVISION_AX) &&
- (dev_priv->vram_type <= VIA_MEM_DDR_200) &&
- (fb->format->depth > 16) &&
- (mode->vdisplay > 768))
- || ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
- (dev_priv->revision == CLE266_REVISION_AX) &&
- (dev_priv->vram_type <= VIA_MEM_DDR_266) &&
- (fb->format->depth > 16) &&
- (mode->hdisplay > 1280))
- || ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
- (dev_priv->revision == CLE266_REVISION_CX) &&
- (mode->hdisplay >= 1024))) {
+ if (enable_extended_display_fifo) {
/* Enable IGA2 extended display FIFO. */
svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
} else {
/* Disable IGA2 extended display FIFO. */
svga_wcrt_mask(VGABASE, 0x6a, 0x00, BIT(5));
}
+ }
+ if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
/* Set IGA2 Display FIFO Depth Select */
reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
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