[Openchrome-devel] drm-openchrome: Branch 'drm-next-4.15' - 4 commits - drivers/gpu/drm
Kevin Brace
kevinbrace at kemper.freedesktop.org
Sun Jan 28 22:46:08 UTC 2018
drivers/gpu/drm/openchrome/via_crtc.c | 60 ++++++++++++++++++++--------------
drivers/gpu/drm/openchrome/via_drv.h | 4 +-
2 files changed, 38 insertions(+), 26 deletions(-)
New commits:
commit b9ad58754850d0bd5d2e45cf7c8c528b7f7f3470
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jan 28 14:45:19 2018 -0800
drm/openchrome: Version bumped to 3.0.67
Display FIFO fixes for P4M800 Pro chipset. Another small adjustment
(PREQ / TREQ control bit) for UniChrome and UniChrome Pro devices.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_drv.h b/drivers/gpu/drm/openchrome/via_drv.h
index 89e312edfe8a..5663ef15adea 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -30,11 +30,11 @@
#define DRIVER_AUTHOR "OpenChrome Project"
#define DRIVER_NAME "openchrome"
#define DRIVER_DESC "OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE "20180127"
+#define DRIVER_DATE "20180128"
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 66
+#define DRIVER_PATCHLEVEL 67
#include <linux/module.h>
commit 6a28ed43a50d6c3c7d92f459c5cc1b9a5731195d
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jan 28 14:41:44 2018 -0800
drm/openchrome: Changing P4M800 Pro IGA1 and IGA2 display FIFO parameters
The display FIFO parameters came from VIA Technologies Chrome IGP open
source DDX device driver. IGA2 parameters were copied from IGA1.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index ec5ac7fa6c6a..5f94a4599f92 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -706,12 +706,18 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
break;
case PCI_DEVICE_ID_VIA_CN700:
- iga->display_queue_expire_num = 0;
- iga->fifo_high_threshold = 64;
- iga->fifo_threshold = 80;
- iga->fifo_max_depth = 96;
- break;
+ /* SR17[7:0] */
+ iga->fifo_max_depth = 128;
+
+ /* SR16[7], SR16[5:0] */
+ iga->fifo_threshold = 32;
+ /* SR18[7], SR18[5:0] */
+ iga->fifo_high_threshold = 56;
+
+ /* SR22[4:0] */
+ iga->display_queue_expire_num = 124;
+ break;
/* CX700 */
case PCI_DEVICE_ID_VIA_VT3157:
iga->fifo_high_threshold = iga->fifo_threshold = 128;
@@ -797,12 +803,6 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
}
}
- /* If resolution > 1280x1024, expire length = 64, else
- expire length = 128 */
- if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CN700) &&
- ((mode->hdisplay > 1280) && (mode->vdisplay > 1024)))
- iga->display_queue_expire_num = 16;
-
/* Set IGA1 Display FIFO Depth Select */
reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
@@ -967,12 +967,18 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
break;
case PCI_DEVICE_ID_VIA_CN700:
- iga->display_queue_expire_num = 128;
- iga->fifo_high_threshold = 32;
- iga->fifo_threshold = 80;
- iga->fifo_max_depth = 96;
- break;
+ /* CR95[7], CR94[7], CR68[7:4] */
+ iga->fifo_max_depth = 128;
+
+ /* CR95[6:4], CR68[3:0] */
+ iga->fifo_threshold = 32;
+ /* CR95[2:0], CR92[3:0] */
+ iga->fifo_high_threshold = 56;
+
+ /* CR94[6:0] */
+ iga->display_queue_expire_num = 124;
+ break;
/* CX700 */
case PCI_DEVICE_ID_VIA_VT3157:
iga->display_queue_expire_num = 128;
@@ -1052,12 +1058,6 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
reg_value = iga->fifo_threshold / 4;
load_value_to_registers(VGABASE, &iga->threshold, reg_value);
} else {
- /* If resolution > 1280x1024, expire length = 64, else
- expire length = 128 */
- if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CN700) &&
- (mode->hdisplay > 1280) && (mode->vdisplay > 1024))
- iga->display_queue_expire_num = 16;
-
/* Set IGA2 Display FIFO Depth Select */
reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
commit 2b1c1ba1b0515def74e5b65247b597ade3dc5de3
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jan 28 14:37:39 2018 -0800
drm/openchrome: Add missing SR22 comments for IGA1
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index 1d4409739948..ec5ac7fa6c6a 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -677,8 +677,10 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
if ((fb->format->depth == 32) &&
(mode->hdisplay >= 1400)) {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 64;
} else {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 128;
}
@@ -695,8 +697,10 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
if ((fb->format->depth == 32) &&
(mode->hdisplay >= 1400)) {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 64;
} else {
+ /* SR22[4:0] */
iga->display_queue_expire_num = 124;
}
commit 1c534a26ee5cc8f87472b251790d4b6739e0d4ca
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sun Jan 28 14:32:25 2018 -0800
drm/openchrome: Actively Set PREQ / TREQ control bit for IGA1
Apparently, this bit is set for many older devices.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index da8322b3e7a8..1d4409739948 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -757,10 +757,18 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
}
if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
- (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
- /* Force PREQ to be always higer than TREQ. */
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_PM800) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_CN700)) {
+ /* Force PREQ to be always higher than TREQ. */
svga_wseq_mask(VGABASE, 0x18, BIT(6), BIT(6));
+ } else {
+ svga_wseq_mask(VGABASE, 0x18, 0x00, BIT(6));
+ }
+ if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
if (enable_extended_display_fifo) {
reg_value = VIA_READ(0x0298);
VIA_WRITE(0x0298, reg_value | 0x20000000);
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