[Pixman] [PATCH 00/10] Cleanups to CPU detection
sandmann at cs.au.dk
Fri Jun 29 14:36:06 PDT 2012
Alan Coopersmith <alan.coopersmith at oracle.com> writes:
> On 06/29/12 01:44 PM, Søren Sandmann Pedersen wrote:
>> I was looking at making use of some of the newer x86 SIMD instruction
>> sets and realized that (a) we don't ever call cpuid on x86-64, we just
>> assume that MMX and SSE2 are present,
> I thought the amd64 ABI guaranteed MMX & SSE2 would always be present - is
> that not the case?
The problem is not so much that assumption, but the fact that for newer
instruction sets such as SSSE3 and AVX, we do need to call cpuid even on
x86-64. So the main point is just preparing the code for that.
But in fact, I'm pretty sure I saw in some Knight's Corner (which is
x86-64) manual, linked from here:
that it doesn't support SSE and MMX, only the new 512 bit vector
instructions. I can't find it now though, so maybe I was
hallucinating. They do say that that chip is not binary compatible with
other x86 chips, and in the instruction manual chapter 4.8, they say
that the state of mm0 through mm7 and xmm0 through xmm7 is "NA".
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