new radeon tiling patch

[Roland Scheidegger]

Alex Deucher wrote:
> On Thu, 13 Jan 2005 15:25:46 +0100, Roland Scheidegger
> <rscheidegger_lists at hispeed.ch> wrote:
> 
>>Ok, here's a new version. It also contains a supposed patch for
>>mergedfb-pageflip (untested, but I need that for color tiling, otherwise
>>I'd need to redo the crtc address calculation in the drm).
>>
>>http://homepage.hispeed.ch/rscheidegger/dri_experimental/radeon_tiling_drm7.diff
>>http://homepage.hispeed.ch/rscheidegger/dri_experimental/radeon_tiling_ddx7.diff
>>http://homepage.hispeed.ch/rscheidegger/dri_experimental/radeon_tiling_dri7.diff
>>
> 
> 
> Roland,
> 
>    I tested with MergedFB and it works perfectly.  Nice speed boost! 
> I must note however, that with pageflipping, the crtc offsets still
> don't seem to propagate down to the drm.  both crtcs end up at zero. 
> that's the same problem I had when I attempted to fix this last week. 
> I don't know why.  Other than that, very nice!

Good to know. btw I should have a new version ready soon (with fixed 
switching from tiled to untiled, and hopefully correct detection of 
mixed tiled/untiled resolutions in mergedfb mode).
You used the drm-core version, right? I've just noticed the non-core 
patch version is broken when looking at it again - that's what you get 
from incomplete copy & paste...

One question I still have though is regarding to the surface setup, I'm 
actually not convinced the addresses are correct in all cases, because I 
don't understand how all that address translation stuff works. So 
currently the addresses which are used always start from 0 (which 
usually is the framebuffer location), but I'm not so sure if that's 
correct for instance for igps regarding how this looks to the gpu.

Roland