AMD/ATI doc question

Pat Kane pekane52 at
Tue Oct 16 14:14:28 PDT 2007


I am trying to grok the AMD/ATI document at
from the bottom up.

The introduction says that register address(es)
are given in the form:
  [aperName:offset]   etc.
And I see that the first memory control register
is specified as:
  MC_SEQ_CNTL - RW - 32 bits - [GpuF0MMReg:0x2600]

Can any one explain what "aperName" and "GpuF0MMReg"
are and how to find out more info about them?

Also, in Appendix A the tables that claim to be
sorted by address are not really sort by the
numerical value of the address, looks more like
the lexical value of the address (i.e  0x2 is
next to 0x2C)


Pat Kane

More information about the xorg mailing list