xf86-video-intel: src/i810_reg.h src/i830_driver.c

[Jesse Barnes]

On Thursday, May 29, 2008 9:23 am Alan Hourihane wrote:
> > You're right, we should be doing a bandwidth calculation based on the
> > current mode for each plane.  But I still don't have access to the
> > spreadsheet that documents how the FIFO should be split, so until then
> > we'll have to hope that stealing all of display plane C's FIFO entries is
> > enough. :)  And at least now we'll know when underruns happen, since I
> > added some debug code.
>
> The way I understand the split to be configured is as so....
>
> e.g. FIFO RAM entries = 96, so...
>
> HDISPLAY for PIPEA = 1280
> HDISPLAY for PIPEB = 1024
>
> Therefore the split is 1280*(96/(1280+1024)) and 1024*(96/(1280+1024))
> giving a value of approx 53 and 43, so DSPARB would be set as....
>
> OUTREG(DSPARB, (95 << DSPARB_CSTART_SHIFT) |
> 		  (52 << DSPARB_BSTART_SHIFT));
>
> Things would need adjusting for FIFO RAM which is 128 or 256 wide,
> obviously.

Well this took way longer than I would have liked it to (going back & forth 
with lots of hw & driver guys for about a month).

Based on what I heard from them, it sounds like reprogramming DSPARB might be 
a bad idea in some cases.  But we actually don't have many bug reports open 
on the issue since we started doing it, so I feel brave enough to try the 
algorithm you outlined here (though strictly speaking it's missing some stuff 
I think it does provide a much better approximation of what we should be 
doing).

I've attached the latest patch (only tested on my T61) for testing to bug 
16169.

Thanks,
Jesse