dri-devel January 2021

dri-devel@lists.freedesktop.org

322 participants
737 discussions

[PATCH 1/1] dma-buf: heaps: Map system heap pages as managed by linux vm
by Suren Baghdasaryan 28 Jan '21

28 Jan '21

Currently system heap maps its buffers with VM_PFNMAP flag using remap_pfn_range. This results in such buffers not being accounted for in PSS calculations because vm treats this memory as having no page structs. Without page structs there are no counters representing how many processes are mapping a page and therefore PSS calculation is impossible. Historically, ION driver used to map its buffers as VM_PFNMAP areas due to memory carveouts that did not have page structs [1]. That is not the case anymore and it seems there was desire to move away from remap_pfn_range [2]. Dmabuf system heap design inherits this ION behavior and maps its pages using remap_pfn_range even though allocated pages are backed by page structs. Clear VM_IO and VM_PFNMAP flags when mapping memory allocated by the system heap and replace remap_pfn_range with vm_insert_page, following Laura's suggestion in [1]. This would allow correct PSS calculation for dmabufs. [1] https://driverdev-devel.linuxdriverproject.narkive.com/v0fJGpaD/using-ion-m… [2] http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2018-Octo… (sorry, could not find lore links for these discussions) Suggested-by: Laura Abbott <labbott(a)kernel.org> Signed-off-by: Suren Baghdasaryan <surenb(a)google.com> --- drivers/dma-buf/heaps/system_heap.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/dma-buf/heaps/system_heap.c b/drivers/dma-buf/heaps/system_heap.c index 17e0e9a68baf..0e92e42b2251 100644 --- a/drivers/dma-buf/heaps/system_heap.c +++ b/drivers/dma-buf/heaps/system_heap.c @@ -200,11 +200,13 @@ static int system_heap_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) struct sg_page_iter piter; int ret; + /* All pages are backed by a "struct page" */ + vma->vm_flags &= ~VM_PFNMAP; + for_each_sgtable_page(table, &piter, vma->vm_pgoff) { struct page *page = sg_page_iter_page(&piter); - ret = remap_pfn_range(vma, addr, page_to_pfn(page), PAGE_SIZE, - vma->vm_page_prot); + ret = vm_insert_page(vma, addr, page); if (ret) return ret; addr += PAGE_SIZE; -- 2.30.0.280.ga3ce27912f-goog

1 1

[RFC PATCH 0/3] add ttm trace event support
by Kevin Wang 28 Jan '21

28 Jan '21

the kernel ftrace can better help analyze the kernel running status. add some trace events to support TTM. add trace events list: ttm:ttm_bo_add_mem_to_lru ttm:ttm_bo_del_from_lru ttm:ttm_bo_move_mem ttm:ttm_bo_wait ttm:ttm_bo_evict ttm:ttm_bo_swapout ttm:ttm_bo_device_init ttm:ttm_bo_device_release ttm:ttm_bo_init_reserved ttm:ttm_bo_validate ttm:ttm_bo_release ttm:ttm_bo_mmap ttm:ttm_bo_vm_fault ttm:ttm_bo_vm_access ttm:ttm_shrink ttm:ttm_mem_global_reserve ttm:ttm_mem_global_free Kevin Wang (3): drm/ttm: add ttm bo trace event support drm/ttm: add ttm vm bo trace event support drm/ttm: add ttm mem trace event support drivers/gpu/drm/ttm/ttm_bo.c | 23 ++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 12 +- drivers/gpu/drm/ttm/ttm_memory.c | 7 + drivers/gpu/drm/ttm/ttm_module.c | 3 + drivers/gpu/drm/ttm/ttm_trace.h | 469 +++++++++++++++++++++++++++++++ 5 files changed, 512 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/ttm/ttm_trace.h -- 2.17.1

3 5

[PATCH v2 1/3] dma-buf: heaps: Add deferred-free-helper library code
by John Stultz 28 Jan '21

28 Jan '21

This patch provides infrastructure for deferring buffer frees. This is a feature ION provided which when used with some form of a page pool, provides a nice performance boost in an allocation microbenchmark. The reason it helps is it allows the page-zeroing to be done out of the normal allocation/free path, and pushed off to a kthread. As not all heaps will find this useful, its implemented as a optional helper library that heaps can utilize. Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: Liam Mark <lmark(a)codeaurora.org> Cc: Chris Goldsworthy <cgoldswo(a)codeaurora.org> Cc: Laura Abbott <labbott(a)kernel.org> Cc: Brian Starkey <Brian.Starkey(a)arm.com> Cc: Hridya Valsaraju <hridya(a)google.com> Cc: Suren Baghdasaryan <surenb(a)google.com> Cc: Sandeep Patil <sspatil(a)google.com> Cc: Daniel Mentz <danielmentz(a)google.com> Cc: Ørjan Eide <orjan.eide(a)arm.com> Cc: Robin Murphy <robin.murphy(a)arm.com> Cc: Ezequiel Garcia <ezequiel(a)collabora.com> Cc: Simon Ser <contact(a)emersion.fr> Cc: James Jones <jajones(a)nvidia.com> Cc: linux-media(a)vger.kernel.org Cc: dri-devel(a)lists.freedesktop.org Signed-off-by: John Stultz <john.stultz(a)linaro.org> --- v2: * Fix sleep in atomic issue from using a mutex, by switching to a spinlock as Reported-by: kernel test robot <oliver.sang(a)intel.com> * Cleanup API to use a reason enum for clarity and add some documentation comments as suggested by Suren Baghdasaryan. --- drivers/dma-buf/heaps/Kconfig | 3 + drivers/dma-buf/heaps/Makefile | 1 + drivers/dma-buf/heaps/deferred-free-helper.c | 136 +++++++++++++++++++ drivers/dma-buf/heaps/deferred-free-helper.h | 55 ++++++++ 4 files changed, 195 insertions(+) create mode 100644 drivers/dma-buf/heaps/deferred-free-helper.c create mode 100644 drivers/dma-buf/heaps/deferred-free-helper.h diff --git a/drivers/dma-buf/heaps/Kconfig b/drivers/dma-buf/heaps/Kconfig index a5eef06c4226..ecf65204f714 100644 --- a/drivers/dma-buf/heaps/Kconfig +++ b/drivers/dma-buf/heaps/Kconfig @@ -1,3 +1,6 @@ +config DMABUF_HEAPS_DEFERRED_FREE + bool + config DMABUF_HEAPS_SYSTEM bool "DMA-BUF System Heap" depends on DMABUF_HEAPS diff --git a/drivers/dma-buf/heaps/Makefile b/drivers/dma-buf/heaps/Makefile index 974467791032..4e7839875615 100644 --- a/drivers/dma-buf/heaps/Makefile +++ b/drivers/dma-buf/heaps/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_DMABUF_HEAPS_DEFERRED_FREE) += deferred-free-helper.o obj-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o obj-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o diff --git a/drivers/dma-buf/heaps/deferred-free-helper.c b/drivers/dma-buf/heaps/deferred-free-helper.c new file mode 100644 index 000000000000..cf04148167a2 --- /dev/null +++ b/drivers/dma-buf/heaps/deferred-free-helper.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Deferred dmabuf freeing helper + * + * Copyright (C) 2020 Linaro, Ltd. + * + * Based on the ION page pool code + * Copyright (C) 2011 Google, Inc. + */ + +#include <linux/freezer.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/swap.h> +#include <linux/sched/signal.h> + +#include "deferred-free-helper.h" + +static LIST_HEAD(free_list); +static size_t list_size; +wait_queue_head_t freelist_waitqueue; +struct task_struct *freelist_task; +static DEFINE_SPINLOCK(free_list_lock); + +void deferred_free(struct deferred_freelist_item *item, + void (*free)(struct deferred_freelist_item*, + enum df_reason), + size_t size) +{ + unsigned long flags; + + INIT_LIST_HEAD(&item->list); + item->size = size; + item->free = free; + + spin_lock_irqsave(&free_list_lock, flags); + list_add(&item->list, &free_list); + list_size += size; + spin_unlock_irqrestore(&free_list_lock, flags); + wake_up(&freelist_waitqueue); +} + +static size_t free_one_item(enum df_reason reason) +{ + unsigned long flags; + size_t size = 0; + struct deferred_freelist_item *item; + + spin_lock_irqsave(&free_list_lock, flags); + if (list_empty(&free_list)) { + spin_unlock_irqrestore(&free_list_lock, flags); + return 0; + } + item = list_first_entry(&free_list, struct deferred_freelist_item, list); + list_del(&item->list); + size = item->size; + list_size -= size; + spin_unlock_irqrestore(&free_list_lock, flags); + + item->free(item, reason); + return size; +} + +static unsigned long get_freelist_size(void) +{ + unsigned long size; + unsigned long flags; + + spin_lock_irqsave(&free_list_lock, flags); + size = list_size; + spin_unlock_irqrestore(&free_list_lock, flags); + return size; +} + +static unsigned long freelist_shrink_count(struct shrinker *shrinker, + struct shrink_control *sc) +{ + return get_freelist_size(); +} + +static unsigned long freelist_shrink_scan(struct shrinker *shrinker, + struct shrink_control *sc) +{ + int total_freed = 0; + + if (sc->nr_to_scan == 0) + return 0; + + while (total_freed < sc->nr_to_scan) { + int freed = free_one_item(DF_UNDER_PRESSURE); + + if (!freed) + break; + + total_freed += freed; + } + + return total_freed; +} + +static struct shrinker freelist_shrinker = { + .count_objects = freelist_shrink_count, + .scan_objects = freelist_shrink_scan, + .seeks = DEFAULT_SEEKS, + .batch = 0, +}; + +static int deferred_free_thread(void *data) +{ + while (true) { + wait_event_freezable(freelist_waitqueue, + get_freelist_size() > 0); + + free_one_item(DF_NORMAL); + } + + return 0; +} + +static int deferred_freelist_init(void) +{ + list_size = 0; + + init_waitqueue_head(&freelist_waitqueue); + freelist_task = kthread_run(deferred_free_thread, NULL, + "%s", "dmabuf-deferred-free-worker"); + if (IS_ERR(freelist_task)) { + pr_err("%s: creating thread for deferred free failed\n", + __func__); + return -1; + } + sched_set_normal(freelist_task, 19); + + return register_shrinker(&freelist_shrinker); +} +device_initcall(deferred_freelist_init); diff --git a/drivers/dma-buf/heaps/deferred-free-helper.h b/drivers/dma-buf/heaps/deferred-free-helper.h new file mode 100644 index 000000000000..2c43dd5a3eda --- /dev/null +++ b/drivers/dma-buf/heaps/deferred-free-helper.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef DEFERRED_FREE_HELPER_H +#define DEFERRED_FREE_HELPER_H + +/** + * df_reason - enum for reason why item was freed + * + * This provides a reason for why the free funciton was called + * on the item. This is useful when deferred_free is used in + * combination with a pagepool, so under pressure the page can + * be immediately freed. + * + * DF_NORMAL: Normal deferred free + * + * DF_UNDER_PRESSURE: Free was called because the system + * is under memory pressure. Usually + * from a shrinker. Avoid allocating + * memory in the free call, as it may + * fail. + */ +enum df_reason { + DF_NORMAL, + DF_UNDER_PRESSURE, +}; + +/** + * deferred_freelist_item - item structure for deferred freelist + * + * This is to be added to the structure for whatever you want to + * defer freeing on. + * + * @size: size of the item to be freed + * @free: function pointer to be called when freeing the item + * @list: list entry for the deferred list + */ +struct deferred_freelist_item { + size_t size; + void (*free)(struct deferred_freelist_item *i, + enum df_reason reason); + struct list_head list; +}; + +/** + * deferred_free - call to add item to the deferred free list + * + * @item: Pointer to deferred_freelist_item field of a structure + * @free: Function pointer to the free call + * @size: Size of the item to be freed + */ +void deferred_free(struct deferred_freelist_item *item, + void (*free)(struct deferred_freelist_item *i, + enum df_reason reason), + size_t size); +#endif -- 2.17.1

2 5

[PATCH v10 0/9] drm/mediatek: add support for mediatek SOC MT8183
by Hsin-Yi Wang 28 Jan '21

28 Jan '21

This series is based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next The series is tested on a mt8183 krane device. Change since v9 - change several function to rebase to mediatek-drm-next Change since v8 - fix some review comment in v8 - separate gamma module for mt8183 has no dither function in gamma - enable dither function for 5 or 6 bpc panel display - separate ddp mutex patch from the whole Soc patch Change since v7 - add dt-binding for mt8183 display - base mmsys patch https://patchwork.kernel.org/project/linux-mediatek/cover/1607506379-10998-… - base dts patch https://patchwork.kernel.org/project/linux-mediatek/cover/20201127104930.19… - add mt8183 function call for setting the routing registers - add RDMA fifo size error handle Change since v6 - move ddp component define into mtk_mmsys.h - add mmsys private data to support different ic path connection - add mt8183-mmsys.c to support 8183 path connection - fix reviewed issue in v6 Change since v5 - fix reviewed issue in v5 base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Hsin-Yi Wang (1): drm/mediatek: generalize mtk_dither_set() function Yongqiang Niu (8): arm64: dts: mt8183: rename rdma fifo size arm64: dts: mt8183: refine gamma compatible name drm/mediatek: add RDMA fifo size error handle drm/mediatek: separate gamma module drm/mediatek: add has_dither private data for gamma drm/mediatek: enable dither function drm/mediatek: add DDP support for MT8183 drm/mediatek: add support for mediatek SOC MT8183 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 14 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 195 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 10 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 131 +++++++------ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 49 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mtk-mutex.c | 50 +++++ 10 files changed, 402 insertions(+), 74 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c -- 2.30.0.280.ga3ce27912f-goog

2 21

[PATCH v3 1/3] dma-buf: heaps: Add deferred-free-helper library code
by John Stultz 28 Jan '21

28 Jan '21

This patch provides infrastructure for deferring buffer frees. This is a feature ION provided which when used with some form of a page pool, provides a nice performance boost in an allocation microbenchmark. The reason it helps is it allows the page-zeroing to be done out of the normal allocation/free path, and pushed off to a kthread. As not all heaps will find this useful, its implemented as a optional helper library that heaps can utilize. Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: Liam Mark <lmark(a)codeaurora.org> Cc: Chris Goldsworthy <cgoldswo(a)codeaurora.org> Cc: Laura Abbott <labbott(a)kernel.org> Cc: Brian Starkey <Brian.Starkey(a)arm.com> Cc: Hridya Valsaraju <hridya(a)google.com> Cc: Suren Baghdasaryan <surenb(a)google.com> Cc: Sandeep Patil <sspatil(a)google.com> Cc: Daniel Mentz <danielmentz(a)google.com> Cc: Ørjan Eide <orjan.eide(a)arm.com> Cc: Robin Murphy <robin.murphy(a)arm.com> Cc: Ezequiel Garcia <ezequiel(a)collabora.com> Cc: Simon Ser <contact(a)emersion.fr> Cc: James Jones <jajones(a)nvidia.com> Cc: linux-media(a)vger.kernel.org Cc: dri-devel(a)lists.freedesktop.org Signed-off-by: John Stultz <john.stultz(a)linaro.org> --- v2: * Fix sleep in atomic issue from using a mutex, by switching to a spinlock as Reported-by: kernel test robot <oliver.sang(a)intel.com> * Cleanup API to use a reason enum for clarity and add some documentation comments as suggested by Suren Baghdasaryan. v3: * Minor tweaks so it can be built as a module * A few small fixups suggested by Daniel Mentz --- drivers/dma-buf/heaps/Kconfig | 3 + drivers/dma-buf/heaps/Makefile | 1 + drivers/dma-buf/heaps/deferred-free-helper.c | 138 +++++++++++++++++++ drivers/dma-buf/heaps/deferred-free-helper.h | 55 ++++++++ 4 files changed, 197 insertions(+) create mode 100644 drivers/dma-buf/heaps/deferred-free-helper.c create mode 100644 drivers/dma-buf/heaps/deferred-free-helper.h diff --git a/drivers/dma-buf/heaps/Kconfig b/drivers/dma-buf/heaps/Kconfig index a5eef06c4226..f7aef8bc7119 100644 --- a/drivers/dma-buf/heaps/Kconfig +++ b/drivers/dma-buf/heaps/Kconfig @@ -1,3 +1,6 @@ +config DMABUF_HEAPS_DEFERRED_FREE + tristate + config DMABUF_HEAPS_SYSTEM bool "DMA-BUF System Heap" depends on DMABUF_HEAPS diff --git a/drivers/dma-buf/heaps/Makefile b/drivers/dma-buf/heaps/Makefile index 974467791032..4e7839875615 100644 --- a/drivers/dma-buf/heaps/Makefile +++ b/drivers/dma-buf/heaps/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_DMABUF_HEAPS_DEFERRED_FREE) += deferred-free-helper.o obj-$(CONFIG_DMABUF_HEAPS_SYSTEM) += system_heap.o obj-$(CONFIG_DMABUF_HEAPS_CMA) += cma_heap.o diff --git a/drivers/dma-buf/heaps/deferred-free-helper.c b/drivers/dma-buf/heaps/deferred-free-helper.c new file mode 100644 index 000000000000..941608319a94 --- /dev/null +++ b/drivers/dma-buf/heaps/deferred-free-helper.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Deferred dmabuf freeing helper + * + * Copyright (C) 2020 Linaro, Ltd. + * + * Based on the ION page pool code + * Copyright (C) 2011 Google, Inc. + */ + +#include <linux/freezer.h> +#include <linux/list.h> +#include <linux/slab.h> +#include <linux/swap.h> +#include <linux/sched/signal.h> + +#include "deferred-free-helper.h" + +static LIST_HEAD(free_list); +static size_t list_size; +wait_queue_head_t freelist_waitqueue; +struct task_struct *freelist_task; +static DEFINE_SPINLOCK(free_list_lock); + +void deferred_free(struct deferred_freelist_item *item, + void (*free)(struct deferred_freelist_item*, + enum df_reason), + size_t size) +{ + unsigned long flags; + + INIT_LIST_HEAD(&item->list); + item->size = size; + item->free = free; + + spin_lock_irqsave(&free_list_lock, flags); + list_add(&item->list, &free_list); + list_size += size; + spin_unlock_irqrestore(&free_list_lock, flags); + wake_up(&freelist_waitqueue); +} +EXPORT_SYMBOL_GPL(deferred_free); + +static size_t free_one_item(enum df_reason reason) +{ + unsigned long flags; + size_t size = 0; + struct deferred_freelist_item *item; + + spin_lock_irqsave(&free_list_lock, flags); + if (list_empty(&free_list)) { + spin_unlock_irqrestore(&free_list_lock, flags); + return 0; + } + item = list_first_entry(&free_list, struct deferred_freelist_item, list); + list_del(&item->list); + size = item->size; + list_size -= size; + spin_unlock_irqrestore(&free_list_lock, flags); + + item->free(item, reason); + return size; +} + +static unsigned long get_freelist_size(void) +{ + unsigned long size; + unsigned long flags; + + spin_lock_irqsave(&free_list_lock, flags); + size = list_size; + spin_unlock_irqrestore(&free_list_lock, flags); + return size; +} + +static unsigned long freelist_shrink_count(struct shrinker *shrinker, + struct shrink_control *sc) +{ + return get_freelist_size(); +} + +static unsigned long freelist_shrink_scan(struct shrinker *shrinker, + struct shrink_control *sc) +{ + unsigned long total_freed = 0; + + if (sc->nr_to_scan == 0) + return 0; + + while (total_freed < sc->nr_to_scan) { + size_t freed = free_one_item(DF_UNDER_PRESSURE); + + if (!freed) + break; + + total_freed += freed; + } + + return total_freed; +} + +static struct shrinker freelist_shrinker = { + .count_objects = freelist_shrink_count, + .scan_objects = freelist_shrink_scan, + .seeks = DEFAULT_SEEKS, + .batch = 0, +}; + +static int deferred_free_thread(void *data) +{ + while (true) { + wait_event_freezable(freelist_waitqueue, + get_freelist_size() > 0); + + free_one_item(DF_NORMAL); + } + + return 0; +} + +static int deferred_freelist_init(void) +{ + list_size = 0; + + init_waitqueue_head(&freelist_waitqueue); + freelist_task = kthread_run(deferred_free_thread, NULL, + "%s", "dmabuf-deferred-free-worker"); + if (IS_ERR(freelist_task)) { + pr_err("Creating thread for deferred free failed\n"); + return -1; + } + sched_set_normal(freelist_task, 19); + + return register_shrinker(&freelist_shrinker); +} +module_init(deferred_freelist_init); +MODULE_LICENSE("GPL v2"); + diff --git a/drivers/dma-buf/heaps/deferred-free-helper.h b/drivers/dma-buf/heaps/deferred-free-helper.h new file mode 100644 index 000000000000..18b44ac86ef6 --- /dev/null +++ b/drivers/dma-buf/heaps/deferred-free-helper.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef DEFERRED_FREE_HELPER_H +#define DEFERRED_FREE_HELPER_H + +/** + * df_reason - enum for reason why item was freed + * + * This provides a reason for why the free function was called + * on the item. This is useful when deferred_free is used in + * combination with a pagepool, so under pressure the page can + * be immediately freed. + * + * DF_NORMAL: Normal deferred free + * + * DF_UNDER_PRESSURE: Free was called because the system + * is under memory pressure. Usually + * from a shrinker. Avoid allocating + * memory in the free call, as it may + * fail. + */ +enum df_reason { + DF_NORMAL, + DF_UNDER_PRESSURE, +}; + +/** + * deferred_freelist_item - item structure for deferred freelist + * + * This is to be added to the structure for whatever you want to + * defer freeing on. + * + * @size: size of the item to be freed + * @free: function pointer to be called when freeing the item + * @list: list entry for the deferred list + */ +struct deferred_freelist_item { + size_t size; + void (*free)(struct deferred_freelist_item *i, + enum df_reason reason); + struct list_head list; +}; + +/** + * deferred_free - call to add item to the deferred free list + * + * @item: Pointer to deferred_freelist_item field of a structure + * @free: Function pointer to the free call + * @size: Size of the item to be freed + */ +void deferred_free(struct deferred_freelist_item *item, + void (*free)(struct deferred_freelist_item *i, + enum df_reason reason), + size_t size); +#endif -- 2.25.1

1 2

[Bug 211349] New: IB test failed on sdma0 ! AMDGPU driver for Raven APU (ryzen 2400G) hangs!
by bugzilla-daemon＠bugzilla.kernel.org 28 Jan '21

28 Jan '21

https://bugzilla.kernel.org/show_bug.cgi?id=211349 Bug ID: 211349 Summary: IB test failed on sdma0 ! AMDGPU driver for Raven APU (ryzen 2400G) hangs! Product: Drivers Version: 2.5 Kernel Version: 5.10.9 Hardware: i386 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: bolando(a)163.com Regression: No When load AMDGPU driver,it hangs everytime with IB test faild on sdma0.The AMDGPU drivers is not support on 32bit system? My linux is LFS-10.0,hardware is mainboard(Biostar B450GT with newest bios,update to 12/08/2020),cpu(Ryzen5 2400G),memery(32G DDR4 with duaul channel).I have test many version of kernels and amdgpu firmware,but hangs every time when modprobe amdgpu. I also have installed Ubuntu 20.4 TLS(with 5.8.0-25 kernel),AMDGPU worked very good on it. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 22

[PATCH v1 0/2] mm: simplify free_highmem_page() and free_reserved_page()
by David Hildenbrand 28 Jan '21

28 Jan '21

Let's simplify and unify free_highmem_page() and free_reserved_page(). Gave it a quick test in i386 QEMU with 4G of RAM - seems to work just fine. David Hildenbrand (2): video: fbdev: acornfb: remove free_unused_pages() mm: simplify free_highmem_page() and free_reserved_page() drivers/video/fbdev/acornfb.c | 34 -------------------------------- include/linux/highmem-internal.h | 5 ----- include/linux/mm.h | 16 ++------------- mm/page_alloc.c | 11 ----------- 4 files changed, 2 insertions(+), 64 deletions(-) -- 2.29.2

4 8

[PATCH v4 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
by Nick Fan 28 Jan '21

28 Jan '21

Add devicetree schema for Arm Mali Valhall GPU Define a compatible string for the Mali Valhall GPU for Mediatek's SoC platform. Signed-off-by: Nick Fan <Nick.Fan(a)mediatek.com> --- .../bindings/gpu/arm,mali-valhall.yaml | 252 ++++++++++++++++++ 1 file changed, 252 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml new file mode 100644 index 000000000000..ecf249a58435 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml @@ -0,0 +1,252 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Mali Valhall GPU + +maintainers: + - Rob Herring <robh(a)kernel.org> + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + + compatible: + items: + - enum: + - mediatek,mt8192-mali + - const: arm,mali-valhall + + reg: + maxItems: 1 + + interrupts: + items: + - description: GPU interrupt + - description: MMU interrupt + - description: Job interrupt + + interrupt-names: + items: + - const: gpu + - const: mmu + - const: job + + clocks: + minItems: 1 + + power-domains: + minItems: 1 + maxItems: 5 + + mali-supply: true + sram-supply: true + + operating-points-v2: true + + "#cooling-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-mali + then: + properties: + sram-supply: true + power-domains: + description: + List of phandle and PM domain specifier as documented in + Documentation/devicetree/bindings/power/power_domain.txt + minItems: 5 + maxItems: 5 + power-domain-names: + items: + - const: core0 + - const: core1 + - const: core2 + - const: core3 + - const: core4 + + required: + - sram-supply + - power-domains + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu@13000000 { + compatible = "mediatek,mt8192-mali", "arm,mali-valhall"; + reg = <0x13000000 0x4000>; + interrupts = + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = + "gpu", + "mmu", + "job"; + + clocks = <&mfgcfg 0>; + + power-domains = + <&spm 4>, + <&spm 5>, + <&spm 6>, + <&spm 7>, + <&spm 8>; + + operating-points-v2 = <&gpu_opp_table>; + mali-supply = <&mt6315_7_vbuck1>; + sram-supply = <&mt6359_vsram_others_ldo_reg>; + }; + + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + opp-hz-real = /bits/ 64 <358000000>, + /bits/ 64 <358000000>; + opp-microvolt = <606250>, + <750000>; + }; + + opp-399000000 { + opp-hz = /bits/ 64 <399000000>; + opp-hz-real = /bits/ 64 <399000000>, + /bits/ 64 <399000000>; + opp-microvolt = <618750>, + <750000>; + }; + + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-hz-real = /bits/ 64 <440000000>, + /bits/ 64 <440000000>; + opp-microvolt = <631250>, + <750000>; + }; + + opp-482000000 { + opp-hz = /bits/ 64 <482000000>; + opp-hz-real = /bits/ 64 <482000000>, + /bits/ 64 <482000000>; + opp-microvolt = <643750>, + <750000>; + }; + + opp-523000000 { + opp-hz = /bits/ 64 <523000000>; + opp-hz-real = /bits/ 64 <523000000>, + /bits/ 64 <523000000>; + opp-microvolt = <656250>, + <750000>; + }; + + opp-564000000 { + opp-hz = /bits/ 64 <564000000>; + opp-hz-real = /bits/ 64 <564000000>, + /bits/ 64 <564000000>; + opp-microvolt = <668750>, + <750000>; + }; + + opp-605000000 { + opp-hz = /bits/ 64 <605000000>; + opp-hz-real = /bits/ 64 <605000000>, + /bits/ 64 <605000000>; + opp-microvolt = <681250>, + <750000>; + }; + + opp-647000000 { + opp-hz = /bits/ 64 <647000000>; + opp-hz-real = /bits/ 64 <647000000>, + /bits/ 64 <647000000>; + opp-microvolt = <693750>, + <750000>; + }; + + opp-688000000 { + opp-hz = /bits/ 64 <688000000>; + opp-hz-real = /bits/ 64 <688000000>, + /bits/ 64 <688000000>; + opp-microvolt = <706250>, + <750000>; + }; + + opp-724000000 { + opp-hz = /bits/ 64 <724000000>; + opp-hz-real = /bits/ 64 <724000000>, + /bits/ 64 <724000000>; + opp-microvolt = <725000>, + <750000>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-hz-real = /bits/ 64 <760000000>, + /bits/ 64 <760000000>; + opp-microvolt = <743750>, + <750000>; + }; + + opp-795000000 { + opp-hz = /bits/ 64 <795000000>; + opp-hz-real = /bits/ 64 <795000000>, + /bits/ 64 <795000000>; + opp-microvolt = <762500>, + <762500>; + }; + + opp-831000000 { + opp-hz = /bits/ 64 <831000000>; + opp-hz-real = /bits/ 64 <831000000>, + /bits/ 64 <831000000>; + opp-microvolt = <781250>, + <781250>; + }; + + opp-855000000 { + opp-hz = /bits/ 64 <855000000>; + opp-hz-real = /bits/ 64 <855000000>, + /bits/ 64 <855000000>; + opp-microvolt = <793750>, + <793750>; + }; + + opp-902000000 { + opp-hz = /bits/ 64 <902000000>; + opp-hz-real = /bits/ 64 <902000000>, + /bits/ 64 <902000000>; + opp-microvolt = <818750>, + <818750>; + }; + + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + opp-hz-real = /bits/ 64 <950000000>, + /bits/ 64 <950000000>; + opp-microvolt = <843750>, + <843750>; + }; + }; +... -- 2.18.0

3 3

[PATCH v3, 00/15] drm/mediatek: add support for mediatek SOC MT8192
by Yongqiang Niu 28 Jan '21

28 Jan '21

This series are based on 5.11-rc1 and SoC MT8183, and provide 15 patch to support mediatek SOC MT8192 Changes since v2: - fix review comment in v2 - add pm runtime for gamma and color - move ddp path select patch to mmsys series - remove some useless patch Yongqiang Niu (15): dt-bindings: mediatek: add description for postmask dt-bindings: mediatek: add description for mt8192 display arm64: dts: mt8192: add display node drm/mediatek: add component OVL_2L2 drm/mediatek: add component POSTMASK drm/mediatek: add component RDMA4 drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase drm/mediatek: check if fb is null drm/mediatek: Add pm runtime support for gamma drm/mediatek: Add pm runtime support for color drm/mediatek: fix aal size config drm/mediatek: separate ccorr module drm/mediatek: add matrix bits private data for ccorr drm/mediatek: add DDP support for MT8192 drm/mediatek: add support for mediatek SOC MT8192 .../bindings/display/mediatek/mediatek,disp.txt | 3 +- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++++++++++ drivers/gpu/drm/mediatek/Makefile | 4 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 245 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 + drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 34 ++- drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 ++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 35 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 98 +-------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 52 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 + 14 files changed, 687 insertions(+), 98 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c -- 1.8.1.1.dirty

4 30

[PULL] drm-intel-next
by Rodrigo Vivi 27 Jan '21

27 Jan '21

Hi Dave and Daniel, Hopefully this is the last pull request towards 5.12. Please notice this contains a drm/framebuffer change needed for supporting clear color support for TGL Render Decompression. Here goes drm-intel-next-2021-01-27: - HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman) - Fix DP vswing settings and handling (Imre, Ville) - Various display code clean-up (Jani, Ville) - Various display refactoring, including split out of pps, aux, and fdi (Ja\ ni, Dave) - Add DG1 missing workarounds (Jose) - Fix display color conversion (Chris, Ville) - Try to guess PCH type even without ISA bridge (Zhenyu) - More backlight refactor (Lyude) - Support two CSC module on gen11 and later (Lee) - Async flips for all ilk+ platforms (Ville) - Clear color support for TGL (RK) - Add a helper to read data from a GEM object page (Imre) - VRR/Adaptive Sync Enabling on DP/eDP for TGL+ (Manasi, Ville Aditya) Thanks, Rodrigo. The following changes since commit fb5cfcaa2efbb4c71abb1dfbc8f4da727e0bfd89: Merge tag 'drm-intel-gt-next-2021-01-14' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-01-15 15:03:36 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-27 for you to fetch changes up to 784953a46589276b38d7e6dcb5ebf7e29db72ff1: drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoder (2021-01-26 16:34:53 -0800) ---------------------------------------------------------------- - HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman) - Fix DP vswing settings and handling (Imre, Ville) - Various display code clean-up (Jani, Ville) - Various display refactoring, including split out of pps, aux, and fdi (Ja\ ni, Dave) - Add DG1 missing workarounds (Jose) - Fix display color conversion (Chris, Ville) - Try to guess PCH type even without ISA bridge (Zhenyu) - More backlight refactor (Lyude) - Support two CSC module on gen11 and later (Lee) - Async flips for all ilk+ platforms (Ville) - Clear color support for TGL (RK) - Add a helper to read data from a GEM object page (Imre) - VRR/Adaptive Sync Enabling on DP/eDP for TGL+ (Manasi, Ville Aditya) ---------------------------------------------------------------- Aditya Swarup (1): drm/i915/display/dp: Attach and set drm connector VRR property Anshuman Gupta (21): drm/i915/hdcp: Update CP property in update_pipe drm/i915/hdcp: Get conn while content_type changed drm/i915/hotplug: Handle CP_IRQ for DP-MST drm/i915/hdcp: No HDCP when encoder is't initialized drm/i915/hdcp: DP MST transcoder for link and stream drm/i915/hdcp: Move HDCP enc status timeout to header drm/i915/hdcp: HDCP stream encryption support drm/i915/hdcp: Configure HDCP1.4 MST steram encryption status drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support drm/i915/hdcp: Pass dig_port to intel_hdcp_init drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len drm/hdcp: Max MST content streams drm/i915/hdcp: MST streams support in hdcp port_data drm/i915/hdcp: Pass connector to check_2_2_link drm/i915/hdcp: Add HDCP 2.2 stream register drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks drm/i915/hdcp: Configure HDCP2.2 MST steram encryption status drm/i915/hdcp: Enable HDCP 2.2 MST support drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES) drm/i915/hdcp: Fix uninitialized symbol Chris Wilson (1): drm/i915/display: Bitwise or the conversion colour specifier together Dave Airlie (3): drm/i915: refactor some crtc code out of intel display. (v2) drm/i915: refactor pll code out into intel_dpll.c drm/i915: split fdi code out from intel_display.c Imre Deak (3): drm/i915/dp: Move intel_dp_set_signal_levels() to intel_dp_link_training.c drm/i915/dp: Fix LTTPR vswing/pre-emp setting in non-transparent mode drm/i915/gem: Add a helper to read data from a GEM object page Jani Nikula (20): drm/i915/display: remove useless use of inline drm/i915/display: fix the uint*_t types that have crept in drm/i915/pps: abstract panel power sequencer from intel_dp.c drm/i915/pps: rename pps_{,un}lock -> intel_pps_{,un}lock drm/i915/pps: rename intel_edp_backlight_* to intel_pps_backlight_* drm/i915/pps: rename intel_edp_panel_* to intel_pps_* drm/i915/pps: rename edp_panel_* to intel_pps_*_unlocked drm/i915/pps: abstract intel_pps_vdd_off_sync drm/i915/pps: add higher level intel_pps_init() call drm/i915/pps: abstract intel_pps_encoder_reset() drm/i915/pps: rename intel_dp_check_edp to intel_pps_check_power_unlocked drm/i915/pps: rename intel_power_sequencer_reset to intel_pps_reset_all drm/i915/pps: add locked intel_pps_wait_power_cycle drm/i915/pps: rename vlv_init_panel_power_sequencer to vlv_pps_init drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functions drm/i915/pps: refactor init abstractions drm/i915/pps: move pps code over from intel_display.c and refactor drm/i915/dp: abstract struct intel_dp pps members to a sub-struct drm/i915/dp: split out aux functionality to intel_dp_aux.c drm/msm/dp: fix build after dp quirk helper change José Roberto de Souza (1): drm/i915/dg1: Apply WA 1409120013 and 14011059788 Lee Shawn C (1): drm/i915: support two CSC module on gen11 and later Lyude Paul (6): drm/i915: Pass port to intel_panel_bl_funcs.get() drm/i915: Keep track of pwm-related backlight hooks separately drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now) drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight drm/dp: Revert "drm/dp: Introduce EDID-based quirks" drm/i915/dp: Don't use DPCD backlights that need PWM enable/disable Manasi Navare (9): drm/i915/display/vrr: Create VRR file and add VRR capability check drm/i915/display/dp: Compute VRR state in atomic_check drm/i915/display/dp: Do not enable PSR if VRR is enabled drm/i915/display/vrr: Configure and enable VRR in modeset enable drm/i915/display/vrr: Send VRR push to flip the frame drm/i915/display/vrr: Disable VRR in modeset disable path drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink drm/i915/display: Add HW state readout for VRR drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoder Radhakrishna Sripada (2): drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color drm/i915/tgl: Add Clear Color support for TGL Render Decompression Rodrigo Vivi (1): Merge drm/drm-next into drm-intel-next Ville Syrjälä (29): drm/i915: Drop one more useless master_transcoder assignment drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4 drm/i915: Disable TRAINING_PATTERN_SET before stopping the TPS transmission drm/i915: Fix the training pattern debug print drm/i915: Fix the PHY compliance test vs. hotplug mishap drm/i915: Drop redundant parens drm/i915: Generalize the async flip capability check drm/i915: Add plane vfuncs to enable/disable flip_done interrupt drm/i915: Move the async_flip bit setup into the .async_flip() hook drm/i915: Reuse the async_flip() hook for the async flip disable w/a drm/i915: Fix ICL MG PHY vswing handling drm/i915: Unify the sanity checks for the buf trans tables drm/i915: Store framestart_delay in dev_priv drm/i915: Extract intel_mode_vblank_start() drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() drm/i915/display: VRR + DRRS cannot be enabled together drm/i915: Rename VRR_CTL reg fields drm/i915/display: Helpers for VRR vblank min and max start drm/i915: Add vrr state dump drm/i915: Fix vblank timestamps with VRR drm/i915: Fix vblank evasion with vrr drm/i915: Extract intel_crtc_ddb_weight() drm/i915: Pass the crtc to skl_compute_dbuf_slices() drm/i915: Introduce intel_dbuf_slice_size() drm/i915: Introduce skl_ddb_entry_for_slices() drm/i915: Add pipe ddb entries into the dbuf state drm/i915: Extract intel_crtc_dbuf_weights() drm/i915: Encapsulate dbuf state handling harder drm/i915: Do a bit more initial readout for dbuf Zhenyu Wang (1): drm/i915: Try to guess PCH type even without ISA bridge drivers/gpu/drm/drm_dp_helper.c | 83 +- drivers/gpu/drm/drm_dp_mst_topology.c | 3 +- drivers/gpu/drm/i915/Makefile | 6 + drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_color.c | 16 + drivers/gpu/drm/i915/display/intel_crtc.c | 325 +++ drivers/gpu/drm/i915/display/intel_crtc.h | 22 + drivers/gpu/drm/i915/display/intel_ddi.c | 81 +- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 2807 ++------------------ drivers/gpu/drm/i915/display/intel_display.h | 6 +- .../gpu/drm/i915/display/intel_display_debugfs.c | 9 +- drivers/gpu/drm/i915/display/intel_display_power.c | 6 +- drivers/gpu/drm/i915/display/intel_display_types.h | 141 +- drivers/gpu/drm/i915/display/intel_dp.c | 2315 +--------------- drivers/gpu/drm/i915/display/intel_dp.h | 10 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 692 +++++ drivers/gpu/drm/i915/display/intel_dp_aux.h | 18 + .../gpu/drm/i915/display/intel_dp_aux_backlight.c | 297 ++- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 186 +- .../gpu/drm/i915/display/intel_dp_link_training.c | 38 +- .../gpu/drm/i915/display/intel_dp_link_training.h | 3 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 12 +- drivers/gpu/drm/i915/display/intel_dpll.c | 1363 ++++++++++ drivers/gpu/drm/i915/display/intel_dpll.h | 23 + .../gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_fdi.c | 683 +++++ drivers/gpu/drm/i915/display/intel_fdi.h | 22 + drivers/gpu/drm/i915/display/intel_hdcp.c | 309 ++- drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- drivers/gpu/drm/i915/display/intel_panel.c | 396 +-- drivers/gpu/drm/i915/display/intel_panel.h | 4 + drivers/gpu/drm/i915/display/intel_pps.c | 1406 ++++++++++ drivers/gpu/drm/i915/display/intel_pps.h | 52 + drivers/gpu/drm/i915/display/intel_psr.c | 12 +- drivers/gpu/drm/i915/display/intel_sprite.c | 67 +- drivers/gpu/drm/i915/display/intel_vrr.c | 209 ++ drivers/gpu/drm/i915/display/intel_vrr.h | 33 + drivers/gpu/drm/i915/gem/i915_gem_object.c | 65 + drivers/gpu/drm/i915/gem/i915_gem_object.h | 8 + drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 20 +- drivers/gpu/drm/i915/i915_irq.c | 81 +- drivers/gpu/drm/i915/i915_irq.h | 3 - drivers/gpu/drm/i915/i915_params.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 63 +- drivers/gpu/drm/i915/intel_pch.c | 39 +- drivers/gpu/drm/i915/intel_pm.c | 554 ++-- drivers/gpu/drm/i915/intel_pm.h | 7 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 6 +- drivers/misc/mei/hdcp/mei_hdcp.c | 3 +- include/drm/drm_dp_helper.h | 21 +- include/drm/drm_hdcp.h | 8 +- include/uapi/drm/drm_fourcc.h | 19 + 56 files changed, 6978 insertions(+), 5616 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.c create mode 100644 drivers/gpu/drm/i915/display/intel_crtc.h create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.c create mode 100644 drivers/gpu/drm/i915/display/intel_dp_aux.h create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.c create mode 100644 drivers/gpu/drm/i915/display/intel_dpll.h create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.c create mode 100644 drivers/gpu/drm/i915/display/intel_fdi.h create mode 100644 drivers/gpu/drm/i915/display/intel_pps.c create mode 100644 drivers/gpu/drm/i915/display/intel_pps.h create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.c create mode 100644 drivers/gpu/drm/i915/display/intel_vrr.h

2 1

← Newer
1
...
23
24
25
26
27
28
29
...
74
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel January 2021