dri-devel January 2021

dri-devel@lists.freedesktop.org

322 participants
737 discussions

[PATCH] drm/vmwgfx: Fix some memory leaks on errors
by Zack Rusin 28 Jan '21

28 Jan '21

Dan noticed some issues with pci_release_region, this builds upon that and fixes some other lingering issues. As part of this we also can stop trying to manually free our managed device; there's no need for it, it will be cleaned up automatically for us. Fixes: 8772c0bb58bb ("drm/vmwgfx: Cleanup pci resource allocation") Signed-off-by: Zack Rusin <zackr(a)vmware.com> Reviewed-by: Martin Krastev <krastevm(a)vmware.com> Reviewed-by: Roland Scheidegger <sroland(a)vmware.com> Reported-by: kernel test robot <lkp(a)intel.com> Reported-by: Dan Carpenter <dan.carpenter(a)oracle.com> --- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index 22f5a9f8a44b..792feb08398b 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c @@ -717,7 +717,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) return ret; ret = vmw_detect_version(dev_priv); if (ret) - return ret; + goto out_no_pci_or_version; mutex_init(&dev_priv->cmdbuf_mutex); mutex_init(&dev_priv->release_mutex); @@ -1014,7 +1014,6 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) if (dev_priv->capabilities & SVGA_CAP_IRQMASK) vmw_irq_uninstall(&dev_priv->drm); out_no_irq: - pci_release_regions(pdev); ttm_object_device_release(&dev_priv->tdev); out_err0: for (i = vmw_res_context; i < vmw_res_max; ++i) @@ -1022,7 +1021,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) if (dev_priv->ctx.staged_bindings) vmw_binding_state_free(dev_priv->ctx.staged_bindings); - kfree(dev_priv); +out_no_pci_or_version: + pci_release_regions(pdev); return ret; } @@ -1060,7 +1060,6 @@ static void vmw_driver_unload(struct drm_device *dev) vmw_fence_manager_takedown(dev_priv->fman); if (dev_priv->capabilities & SVGA_CAP_IRQMASK) vmw_irq_uninstall(&dev_priv->drm); - pci_release_regions(pdev); ttm_object_device_release(&dev_priv->tdev); if (dev_priv->ctx.staged_bindings) @@ -1069,7 +1068,7 @@ static void vmw_driver_unload(struct drm_device *dev) for (i = vmw_res_context; i < vmw_res_max; ++i) idr_destroy(&dev_priv->res_idr[i]); - kfree(dev_priv); + pci_release_regions(pdev); } static void vmw_postclose(struct drm_device *dev, -- 2.27.0

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[PATCHv2] drm/msm/kms: Make a lock_class_key for each crtc mutex
by Stephen Boyd 28 Jan '21

28 Jan '21

Lockdep complains about an AA deadlock when rebooting the device. ============================================ WARNING: possible recursive locking detected 5.4.91 #1 Not tainted -------------------------------------------- reboot/5213 is trying to acquire lock: ffffff80d13391b0 (&kms->commit_lock[i]){+.+.}, at: lock_crtcs+0x60/0xa4 but task is already holding lock: ffffff80d1339110 (&kms->commit_lock[i]){+.+.}, at: lock_crtcs+0x60/0xa4 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&kms->commit_lock[i]); lock(&kms->commit_lock[i]); *** DEADLOCK *** May be due to missing lock nesting notation 6 locks held by reboot/5213: __arm64_sys_reboot+0x148/0x2a0 device_shutdown+0x10c/0x2c4 drm_atomic_helper_shutdown+0x48/0xfc modeset_lock+0x120/0x24c lock_crtcs+0x60/0xa4 stack backtrace: CPU: 4 PID: 5213 Comm: reboot Not tainted 5.4.91 #1 Hardware name: Google Pompom (rev1) with LTE (DT) Call trace: dump_backtrace+0x0/0x1dc show_stack+0x24/0x30 dump_stack+0xfc/0x1a8 __lock_acquire+0xcd0/0x22b8 lock_acquire+0x1ec/0x240 __mutex_lock_common+0xe0/0xc84 mutex_lock_nested+0x48/0x58 lock_crtcs+0x60/0xa4 msm_atomic_commit_tail+0x348/0x570 commit_tail+0xdc/0x178 drm_atomic_helper_commit+0x160/0x168 drm_atomic_commit+0x68/0x80 This is because lockdep thinks all the locks taken in lock_crtcs() are the same lock, when they actually aren't. That's because we call mutex_init() in msm_kms_init() and that assigns one static key for every lock initialized in this loop. Let's allocate a dynamic number of lock_class_keys and assign them to each lock so that lockdep can figure out an AA deadlock isn't possible here. Fixes: b3d91800d9ac ("drm/msm: Fix race condition in msm driver with async layer updates") Cc: Krishna Manikandan <mkrishn(a)codeaurora.org> Signed-off-by: Stephen Boyd <swboyd(a)chromium.org> --- Changes from v1: * Fixed typo in commit text drivers/gpu/drm/msm/msm_kms.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index d8151a89e163..4735251a394d 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -157,6 +157,7 @@ struct msm_kms { * from the crtc's pending_timer close to end of the frame: */ struct mutex commit_lock[MAX_CRTCS]; + struct lock_class_key commit_lock_keys[MAX_CRTCS]; unsigned pending_crtc_mask; struct msm_pending_timer pending_timers[MAX_CRTCS]; }; @@ -166,8 +167,11 @@ static inline int msm_kms_init(struct msm_kms *kms, { unsigned i, ret; - for (i = 0; i < ARRAY_SIZE(kms->commit_lock); i++) - mutex_init(&kms->commit_lock[i]); + for (i = 0; i < ARRAY_SIZE(kms->commit_lock); i++) { + lockdep_register_key(&kms->commit_lock_keys[i]); + __mutex_init(&kms->commit_lock[i], "&kms->commit_lock[i]", + &kms->commit_lock_keys[i]); + } kms->funcs = funcs; base-commit: 19c329f6808995b142b3966301f217c831e7cf31 -- https://chromeos.dev

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[PATCH v7 0/2] Add a Himax HX8837 display controller driver
by Lubomir Rintel 28 Jan '21

28 Jan '21

Hi, please take a look at the patches chained to this messages and consider applying them. They add support for the controller that drives the panel on the OLPC XO laptops. Compared to v7, points risen in review by Laurent Pinchart have been addressed. Details in change log of patch 1/2. Tested on an OLPC XO-1.75 laptop. Thank you Lubo

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[PATCH v10] staging: fbtft: add tearing signal detect
by Carlis 28 Jan '21

28 Jan '21

From: zhangxuezhi <zhangxuezhi1(a)yulong.com> For st7789v ic,when we need continuous full screen refresh, it is best to wait for the TE signal arrive to avoid screen tearing Signed-off-by: zhangxuezhi <zhangxuezhi1(a)yulong.com> --- v10: additional notes v9: change pr_* to dev_* v8: delete a log line v7: return error value when request fail v6: add te gpio request fail deal logic v5: fix log print v4: modify some code style and change te irq set function name v3: modify author and signed-off-by name v2: add release te gpio after irq request fail --- drivers/staging/fbtft/fb_st7789v.c | 132 ++++++++++++++++++++++++++++++++++++- drivers/staging/fbtft/fbtft.h | 1 + 2 files changed, 132 insertions(+), 1 deletion(-) diff --git a/drivers/staging/fbtft/fb_st7789v.c b/drivers/staging/fbtft/fb_st7789v.c index 3a280cc..cba08a8 100644 --- a/drivers/staging/fbtft/fb_st7789v.c +++ b/drivers/staging/fbtft/fb_st7789v.c @@ -9,9 +9,12 @@ #include <linux/delay.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/mutex.h> +#include <linux/interrupt.h> +#include <linux/completion.h> #include <linux/module.h> #include <video/mipi_display.h> - +#include <linux/gpio/consumer.h> #include "fbtft.h" #define DRVNAME "fb_st7789v" @@ -66,6 +69,32 @@ enum st7789v_command { #define MADCTL_MX BIT(6) /* bitmask for column address order */ #define MADCTL_MY BIT(7) /* bitmask for page address order */ +#define SPI_PANEL_TE_TIMEOUT 400 /* msecs */ +static struct mutex te_mutex;/* mutex for set te gpio irq status */ +static struct completion spi_panel_te; + +static irqreturn_t spi_panel_te_handler(int irq, void *data) +{ + complete(&spi_panel_te); + return IRQ_HANDLED; +} + +static void set_spi_panel_te_irq_status(struct fbtft_par *par, bool enable) +{ + static int te_irq_count; + + mutex_lock(&te_mutex); + + if (enable) { + if (++te_irq_count == 1) + enable_irq(gpiod_to_irq(par->gpio.te)); + } else { + if (--te_irq_count == 0) + disable_irq(gpiod_to_irq(par->gpio.te)); + } + mutex_unlock(&te_mutex); +} + /** * init_display() - initialize the display controller * @@ -82,6 +111,33 @@ enum st7789v_command { */ static int init_display(struct fbtft_par *par) { + int rc; + struct device *dev = par->info->device; + + par->gpio.te = devm_gpiod_get_index_optional(dev, "te", 0, GPIOD_IN); + if (IS_ERR(par->gpio.te)) { + rc = PTR_ERR(par->gpio.te); + dev_err(par->info->device, "Failed to request te gpio: %d\n", rc); + return rc; + } + if (par->gpio.te) { + init_completion(&spi_panel_te); + mutex_init(&te_mutex); + rc = devm_request_irq(dev, + gpiod_to_irq(par->gpio.te), + spi_panel_te_handler, IRQF_TRIGGER_RISING, + "TE_GPIO", par); + if (rc) { + dev_err(par->info->device, "TE request_irq failed.\n"); + devm_gpiod_put(dev, par->gpio.te); + return rc; + } + + disable_irq_nosync(gpiod_to_irq(par->gpio.te)); + } else { + dev_info(par->info->device, "%s:%d, TE gpio not specified\n", + __func__, __LINE__); + } /* turn off sleep mode */ write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); mdelay(120); @@ -137,6 +193,9 @@ static int init_display(struct fbtft_par *par) */ write_reg(par, PWCTRL1, 0xA4, 0xA1); + /*Tearing Effect Line On*/ + if (par->gpio.te) + write_reg(par, 0x35, 0x00); write_reg(par, MIPI_DCS_SET_DISPLAY_ON); if (HSD20_IPS) @@ -145,6 +204,76 @@ static int init_display(struct fbtft_par *par) return 0; } +/***************************************************************************** + * + * int (*write_vmem)(struct fbtft_par *par); + * + *****************************************************************************/ + +/* 16 bit pixel over 8-bit databus */ +static int st7789v_write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len) +{ + u16 *vmem16; + __be16 *txbuf16 = par->txbuf.buf; + size_t remain; + size_t to_copy; + size_t tx_array_size; + int i; + int ret = 0; + size_t startbyte_size = 0; + + fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "st7789v ---%s(offset=%zu, len=%zu)\n", + __func__, offset, len); + + remain = len / 2; + vmem16 = (u16 *)(par->info->screen_buffer + offset); + + if (par->gpio.dc) + gpiod_set_value(par->gpio.dc, 1); + + /* non buffered write */ + if (!par->txbuf.buf) + return par->fbtftops.write(par, vmem16, len); + + /* buffered write */ + tx_array_size = par->txbuf.len / 2; + + if (par->startbyte) { + txbuf16 = par->txbuf.buf + 1; + tx_array_size -= 2; + *(u8 *)(par->txbuf.buf) = par->startbyte | 0x2; + startbyte_size = 1; + } + + while (remain) { + to_copy = min(tx_array_size, remain); + dev_dbg(par->info->device, " to_copy=%zu, remain=%zu\n", + to_copy, remain - to_copy); + + for (i = 0; i < to_copy; i++) + txbuf16[i] = cpu_to_be16(vmem16[i]); + + vmem16 = vmem16 + to_copy; + if (par->gpio.te) { + set_spi_panel_te_irq_status(par, true); + reinit_completion(&spi_panel_te); + ret = wait_for_completion_timeout(&spi_panel_te, + msecs_to_jiffies(SPI_PANEL_TE_TIMEOUT)); + if (ret == 0) + dev_err(par->info->device, "wait panel TE time out\n"); + } + ret = par->fbtftops.write(par, par->txbuf.buf, + startbyte_size + to_copy * 2); + if (par->gpio.te) + set_spi_panel_te_irq_status(par, false); + if (ret < 0) + return ret; + remain -= to_copy; + } + + return ret; +} + /** * set_var() - apply LCD properties like rotation and BGR mode * @@ -259,6 +388,7 @@ static int blank(struct fbtft_par *par, bool on) .gamma = HSD20_IPS_GAMMA, .fbtftops = { .init_display = init_display, + .write_vmem = st7789v_write_vmem16_bus8, .set_var = set_var, .set_gamma = set_gamma, .blank = blank, diff --git a/drivers/staging/fbtft/fbtft.h b/drivers/staging/fbtft/fbtft.h index 76f8c09..93bac05 100644 --- a/drivers/staging/fbtft/fbtft.h +++ b/drivers/staging/fbtft/fbtft.h @@ -212,6 +212,7 @@ struct fbtft_par { struct gpio_desc *wr; struct gpio_desc *latch; struct gpio_desc *cs; + struct gpio_desc *te; struct gpio_desc *db[16]; struct gpio_desc *led[16]; struct gpio_desc *aux[16]; -- 1.9.1

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[PULL] drm-intel-fixes
by Jani Nikula 28 Jan '21

28 Jan '21

Hi Dave & Daniel - Apparently there's a regression in -rc5 that affects a large portion of the platforms in CI. See [1]. The issue showed up in -rc5 i.e. *before* the changes in this pull, however the issue prevents getting full coverage [2]. It does not look like this pull makes matters worse, but this does not make them better either. BR, Jani. [1] http://lore.kernel.org/r/871re5jiu3.fsf@intel.com [2] https://intel-gfx-ci.01.org/tree/drm-intel-fixes/index.html? drm-intel-fixes-2021-01-28: drm/i915 fixes for v5.11-rc6: - Fix ICL MG PHY vswing - Fix subplatform handling - Fix selftest memleak - Clear CACHE_MODE prior to clearing residuals - Always flush the active worker before returning from the wait - Always try to reserve GGTT address 0x0 The following changes since commit 6ee1d745b7c9fd573fba142a2efdad76a9f1cb04: Linux 5.11-rc5 (2021-01-24 16:47:14 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-01-28 for you to fetch changes up to 489140b5ba2e7cc4b853c29e0591895ddb462a82: drm/i915/gt: Always try to reserve GGTT address 0x0 (2021-01-26 15:45:54 +0200) ---------------------------------------------------------------- drm/i915 fixes for v5.11-rc6: - Fix ICL MG PHY vswing - Fix subplatform handling - Fix selftest memleak - Clear CACHE_MODE prior to clearing residuals - Always flush the active worker before returning from the wait - Always try to reserve GGTT address 0x0 ---------------------------------------------------------------- Chris Wilson (3): drm/i915/gt: Clear CACHE_MODE prior to clearing residuals drm/i915: Always flush the active worker before returning from the wait drm/i915/gt: Always try to reserve GGTT address 0x0 Pan Bian (1): drm/i915/selftest: Fix potential memory leak Umesh Nerlige Ramappa (1): drm/i915: Check for all subplatform bits Ville Syrjälä (1): drm/i915: Fix ICL MG PHY vswing handling drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++-- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 12 +++++++ drivers/gpu/drm/i915/gt/intel_ggtt.c | 47 ++++++++++++++++++++------- drivers/gpu/drm/i915/i915_active.c | 28 ++++++++-------- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +- 6 files changed, 67 insertions(+), 31 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center

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[PATCH v2] drm/amdkfd: dqm fence memory corruption
by Qu Huang 28 Jan '21

28 Jan '21

Amdgpu driver uses 4-byte data type as DQM fence memory, and transmits GPU address of fence memory to microcode through query status PM4 message. However, query status PM4 message definition and microcode processing are all processed according to 8 bytes. Fence memory only allocates 4 bytes of memory, but microcode does write 8 bytes of memory, so there is a memory corruption. Changes since v1: * Change dqm->fence_addr as a u64 pointer to fix this issue, also fix up query_status and amdkfd_fence_wait_timeout function uses 64 bit fence value to make them consistent. Signed-off-by: Qu Huang <jinsdb(a)126.com> --- drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 ++++---- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c index b258a3d..159add0f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c @@ -155,7 +155,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev, /* Wait till CP writes sync code: */ status = amdkfd_fence_wait_timeout( - (unsigned int *) rm_state, + rm_state, QUEUESTATE__ACTIVE, 1500); kfd_gtt_sa_free(dbgdev->dev, mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index e686ce2..4598a9a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1167,7 +1167,7 @@ static int start_cpsch(struct device_queue_manager *dqm) if (retval) goto fail_allocate_vidmem; - dqm->fence_addr = dqm->fence_mem->cpu_ptr; + dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr; dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr; init_interrupts(dqm); @@ -1340,8 +1340,8 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, return retval; } -int amdkfd_fence_wait_timeout(unsigned int *fence_addr, - unsigned int fence_value, +int amdkfd_fence_wait_timeout(uint64_t *fence_addr, + uint64_t fence_value, unsigned int timeout_ms) { unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 16262e5..16b23dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -192,7 +192,7 @@ struct device_queue_manager { uint16_t vmid_pasid[VMID_NUM]; uint64_t pipelines_addr; uint64_t fence_gpu_addr; - unsigned int *fence_addr; + uint64_t *fence_addr; struct kfd_mem_obj *fence_mem; bool active_runlist; int sched_policy; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c index 5d541e0..f71a7fa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c @@ -347,7 +347,7 @@ int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues) } int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, - uint32_t fence_value) + uint64_t fence_value) { uint32_t *buffer, size; int retval = 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c index dfaf771..e3ba0cd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c @@ -283,7 +283,7 @@ static int pm_unmap_queues_v9(struct packet_manager *pm, uint32_t *buffer, } static int pm_query_status_v9(struct packet_manager *pm, uint32_t *buffer, - uint64_t fence_address, uint32_t fence_value) + uint64_t fence_address, uint64_t fence_value) { struct pm4_mes_query_status *packet; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c index a852e0d..08442e7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c @@ -263,7 +263,7 @@ static int pm_unmap_queues_vi(struct packet_manager *pm, uint32_t *buffer, } static int pm_query_status_vi(struct packet_manager *pm, uint32_t *buffer, - uint64_t fence_address, uint32_t fence_value) + uint64_t fence_address, uint64_t fence_value) { struct pm4_mes_query_status *packet; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 09599ef..f304d1f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1003,8 +1003,8 @@ int pqm_get_wave_state(struct process_queue_manager *pqm, u32 *ctl_stack_used_size, u32 *save_area_used_size); -int amdkfd_fence_wait_timeout(unsigned int *fence_addr, - unsigned int fence_value, +int amdkfd_fence_wait_timeout(uint64_t *fence_addr, + uint64_t fence_value, unsigned int timeout_ms); /* Packet Manager */ @@ -1040,7 +1040,7 @@ struct packet_manager_funcs { uint32_t filter_param, bool reset, unsigned int sdma_engine); int (*query_status)(struct packet_manager *pm, uint32_t *buffer, - uint64_t fence_address, uint32_t fence_value); + uint64_t fence_address, uint64_t fence_value); int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer); /* Packet sizes */ @@ -1062,7 +1062,7 @@ int pm_send_set_resources(struct packet_manager *pm, struct scheduling_resources *res); int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues); int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address, - uint32_t fence_value); + uint64_t fence_value); int pm_send_unmap_queue(struct packet_manager *pm, enum kfd_queue_type type, enum kfd_unmap_queues_filter mode, -- 1.8.3.1

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[PATCH v4 0/3] drm/bridge/lontium-lt9611uxc: fix handling of EDID/HPD
by Dmitry Baryshkov 28 Jan '21

28 Jan '21

These three patches provide fixes for HPD handling and EDID readout for Lontium lt9611uxc DSI-to-HDMI bridge driver. Changes since v3: - Protect hdmi_connected using ocm_mutex - Remove !! conversion from int to boolean - Add missing Reviewed-by tags. Changes since v2: - Declare lt9611uxc_hpd_work as static Changes since v1: - Split first patch into two smaller patches - Add Fixes tags Dmitry Baryshkov (3): drm/bridge/lontium-lt9611uxc: fix waiting for EDID to become available drm/bridge/lontium-lt9611uxc: fix get_edid return code drm/bridge/lontium-lt9611uxc: move HPD notification out of IRQ handler

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[PATCH v11 0/9] drm/mediatek: add support for mediatek SOC MT8183
by Hsin-Yi Wang 28 Jan '21

28 Jan '21

This series is based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next The series is tested on a mt8183 krane device. Change since v10 - fix review comments in v9 Change since v9 - change several function to rebase to mediatek-drm-next Change since v8 - fix some review comment in v8 - separate gamma module for mt8183 has no dither function in gamma - enable dither function for 5 or 6 bpc panel display - separate ddp mutex patch from the whole Soc patch Change since v7 - add dt-binding for mt8183 display - base mmsys patch https://patchwork.kernel.org/project/linux-mediatek/cover/1607506379-10998-… - base dts patch https://patchwork.kernel.org/project/linux-mediatek/cover/20201127104930.19… - add mt8183 function call for setting the routing registers - add RDMA fifo size error handle Change since v6 - move ddp component define into mtk_mmsys.h - add mmsys private data to support different ic path connection - add mt8183-mmsys.c to support 8183 path connection - fix reviewed issue in v6 Change since v5 - fix reviewed issue in v5 base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Hsin-Yi Wang (1): drm/mediatek: add mtk_dither_set_common() function Yongqiang Niu (8): arm64: dts: mt8183: rename rdma fifo size arm64: dts: mt8183: refine gamma compatible name drm/mediatek: add RDMA fifo size error handle drm/mediatek: separate gamma module drm/mediatek: add has_dither private data for gamma drm/mediatek: enable dither function soc: mediatek: add mtk mutex support for MT8183 drm/mediatek: add support for mediatek SOC MT8183 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 14 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 196 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 10 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 138 +++++++------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 49 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mtk-mutex.c | 50 +++++ 10 files changed, 410 insertions(+), 74 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c -- 2.30.0.280.ga3ce27912f-goog

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[PATCH] drm/lima: add governor data with pre-defined thresholds
by Christian Hewitt 28 Jan '21

28 Jan '21

This patch adapts the panfrost pre-defined thresholds change [0] to the lima driver to improve real-world performance. The upthreshold value has been set to ramp GPU frequency to max freq faster (compared to panfrost) to compensate for the lower overall performance of utgard devices. [0] https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1… Signed-off-by: Christian Hewitt <christianshewitt(a)gmail.com> --- I have been using Kodi as my test application. If you scroll in library views with hundreds of list items and the panfrost values the slow GPU ramp up is quite noticeable and the GUI feels sluggish. As everything lima runs on is inherently slower than panfrost using devices I believe it's better to ramp up to max freq quicker. drivers/gpu/drm/lima/lima_devfreq.c | 10 +++++++++- drivers/gpu/drm/lima/lima_devfreq.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c index 5686ad4aaf7c..c9854315a0b5 100644 --- a/drivers/gpu/drm/lima/lima_devfreq.c +++ b/drivers/gpu/drm/lima/lima_devfreq.c @@ -163,8 +163,16 @@ int lima_devfreq_init(struct lima_device *ldev) lima_devfreq_profile.initial_freq = cur_freq; dev_pm_opp_put(opp); + /* + * Setup default thresholds for the simple_ondemand governor. + * The values are chosen based on experiments. + */ + ldevfreq->gov_data.upthreshold = 20; + ldevfreq->gov_data.downdifferential = 5; + devfreq = devm_devfreq_add_device(dev, &lima_devfreq_profile, - DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &ldevfreq->gov_data); if (IS_ERR(devfreq)) { dev_err(dev, "Couldn't initialize GPU devfreq\n"); ret = PTR_ERR(devfreq); diff --git a/drivers/gpu/drm/lima/lima_devfreq.h b/drivers/gpu/drm/lima/lima_devfreq.h index 2d9b3008ce77..b0c7c736e81a 100644 --- a/drivers/gpu/drm/lima/lima_devfreq.h +++ b/drivers/gpu/drm/lima/lima_devfreq.h @@ -4,6 +4,7 @@ #ifndef __LIMA_DEVFREQ_H__ #define __LIMA_DEVFREQ_H__ +#include <linux/devfreq.h> #include <linux/spinlock.h> #include <linux/ktime.h> @@ -18,6 +19,7 @@ struct lima_devfreq { struct opp_table *clkname_opp_table; struct opp_table *regulators_opp_table; struct thermal_cooling_device *cooling; + struct devfreq_simple_ondemand_data gov_data; ktime_t busy_time; ktime_t idle_time; -- 2.17.1

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[PATCH 1/2] dt-bindings: panel-simple: add samsung,s6e3fa2 panel
by Iskren Chernev 28 Jan '21

28 Jan '21

Add samsung,s6e3fa2 in the allowed simple-panel compat strings. Signed-off-by: Iskren Chernev <iskren.chernev(a)gmail.com> --- .../devicetree/bindings/display/panel/panel-simple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 27fffafe5b5c0..52480ca230c7b 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -241,6 +241,8 @@ properties: - samsung,ltn101nt05 # Samsung Electronics 14" WXGA (1366x768) TFT LCD panel - samsung,ltn140at29-301 + # Samsung Electronics 5.1" (1920x1080) AMOLED cmd panel + - samsung,s6e3fa2 # Satoz SAT050AT40H12R2 5.0" WVGA TFT LCD panel - satoz,sat050at40h12r2 # Sharp LQ035Q7DB03 3.5" QVGA TFT LCD panel base-commit: d7a03a44a5e93f39ece70ec75d25c6088caa0fdb -- 2.29.2

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dri-devel January 2021