dri-devel January 2021

dri-devel@lists.freedesktop.org

322 participants
737 discussions

[PATCH] drm/ast: Disable fast reset after DRAM initial
by KuoHsiang Chou 19 Jan '21

19 Jan '21

[Bug][AST2500] When AST2500 acts as stand-alone VGA so that DRAM and DVO initialization have to be achieved by VGA driver with P2A (PCI to AHB) enabling. However, HW suggests disable Fast reset mode after DRAM initializaton, because fast reset mode is mainly designed for ARM ICE debugger. Once Fast reset is checked as enabling, WDT (Watch Dog Timer) should be first enabled to avoid system deadlock before disable fast reset mode. Signed-off-by: KuoHsiang Chou <kuohsiang_chou(a)aspeedtech.com> --- drivers/gpu/drm/ast/ast_drv.h | 1 + drivers/gpu/drm/ast/ast_main.c | 4 ++ drivers/gpu/drm/ast/ast_post.c | 72 ++++++++++++++++++++++------------ 3 files changed, 51 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h index da6dfb677540..8bdd1482370d 100644 --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h @@ -320,6 +320,7 @@ bool ast_is_vga_enabled(struct drm_device *dev); void ast_post_gpu(struct drm_device *dev); u32 ast_mindwm(struct ast_private *ast, u32 r); void ast_moutdwm(struct ast_private *ast, u32 r, u32 v); +void patch_ahb_ast2500(struct ast_private *ast); /* ast dp501 */ void ast_set_dp501_video_output(struct drm_device *dev, u8 mode); bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size); diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c index 3775fe26f792..3c072c6589a2 100644 --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c @@ -96,6 +96,10 @@ static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { + /* Patch AST2500 */ + if (((dev->pdev->revision & 0xF0) == 0x40) && ((jregd0 & 0xC0) == 0)) + patch_ahb_ast2500(ast); + /* Double check it's actually working */ data = ast_read32(ast, 0xf004); if (data != 0xFFFFFFFF) { diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index 8902c2f84bf9..2d121c5b2233 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -2026,6 +2026,33 @@ static bool ast_dram_init_2500(struct ast_private *ast) return true; } +void patch_ahb_ast2500(struct ast_private *ast) +{ + u32 data; + +patch_ahb_lock: + /* Clear bus lock condition */ + ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); + ast_moutdwm(ast, 0x1e600084, 0x00010000); + ast_moutdwm(ast, 0x1e600088, 0x00000000); + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + data = ast_mindwm(ast, 0x1e6e2070); + if (data & 0x08000000) { /* check fast reset */ + + ast_moutdwm(ast, 0x1E785004, 0x00000010); + ast_moutdwm(ast, 0x1E785008, 0x00004755); + ast_moutdwm(ast, 0x1E78500c, 0x00000033); + udelay(1000); + } + ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); + do { + data = ast_mindwm(ast, 0x1e6e2000); + if (data == 0xffffffff) + goto patch_ahb_lock; + } while (data != 1); + ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */ +} + void ast_post_chip_2500(struct drm_device *dev) { struct ast_private *ast = to_ast_private(dev); @@ -2033,39 +2060,32 @@ void ast_post_chip_2500(struct drm_device *dev) u8 reg; reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); - if ((reg & 0x80) == 0) {/* vga only */ + if ((reg & 0xC0) == 0) {/* vga only */ /* Clear bus lock condition */ - ast_moutdwm(ast, 0x1e600000, 0xAEED1A03); - ast_moutdwm(ast, 0x1e600084, 0x00010000); - ast_moutdwm(ast, 0x1e600088, 0x00000000); - ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8); - ast_write32(ast, 0xf004, 0x1e6e0000); - ast_write32(ast, 0xf000, 0x1); - ast_write32(ast, 0x12000, 0x1688a8a8); - while (ast_read32(ast, 0x12000) != 0x1) - ; - - ast_write32(ast, 0x10000, 0xfc600309); - while (ast_read32(ast, 0x10000) != 0x1) - ; + patch_ahb_ast2500(ast); + + /* Disable watchdog */ + ast_moutdwm(ast, 0x1E78502C, 0x00000000); + ast_moutdwm(ast, 0x1E78504C, 0x00000000); + /* Reset USB port */ + ast_moutdwm(ast, 0x1E6E2090, 0x20000000); /* add at V1.2 */ + ast_moutdwm(ast, 0x1E6E2094, 0x00004000); /* add at V1.2 */ + if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) { /* add at V1.2 */ + ast_moutdwm(ast, 0x1E6E207C, 0x00800000); /* add at V1.2 */ + mdelay(100); /* add at V1.2 */ + ast_moutdwm(ast, 0x1E6E2070, 0x00800000); /* add at V1.2 */ + } /* add at V1.2 */ + /* Modify eSPI reset pin */ + temp = ast_mindwm(ast, 0x1E6E2070); /* add at V1.3 */ + if (temp & 0x02000000) { /* add at V1.3 */ + ast_moutdwm(ast, 0x1E6E207C, 0x00004000); /* add at V1.3 */ + } /* Slow down CPU/AHB CLK in VGA only mode */ temp = ast_read32(ast, 0x12008); temp |= 0x73; ast_write32(ast, 0x12008, temp); - /* Reset USB port to patch USB unknown device issue */ - ast_moutdwm(ast, 0x1e6e2090, 0x20000000); - temp = ast_mindwm(ast, 0x1e6e2094); - temp |= 0x00004000; - ast_moutdwm(ast, 0x1e6e2094, temp); - temp = ast_mindwm(ast, 0x1e6e2070); - if (temp & 0x00800000) { - ast_moutdwm(ast, 0x1e6e207c, 0x00800000); - mdelay(100); - ast_moutdwm(ast, 0x1e6e2070, 0x00800000); - } - if (!ast_dram_init_2500(ast)) drm_err(dev, "DRAM init failed !\n"); -- 2.18.4

3 4

[PATCH 5/5] drm/nouveau/kms/nv140-: Add CRC methods to gv100_disp_core_mthd_head
by Lyude Paul 19 Jan '21

19 Jan '21

Noticed this while trying to figure out the bit that we need to set in order to get cursor CRCs to come up correctly on volta+: we never actually went and added these methods to gv100_disp_core_mthd_head in drm/nouveau/nvkm/engine/disp/coregv100.c which means we don't trace their values when disp tracing is enabled in nvkm. So, fix that. Cc: Martin Peres <martin.peres(a)free.fr> Cc: Jeremy Cline <jcline(a)redhat.com> Cc: Simon Ser <contact(a)emersion.fr> Signed-off-by: Lyude Paul <lyude(a)redhat.com> --- drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c index e20a48f201f6..448a515057c7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c @@ -106,6 +106,8 @@ gv100_disp_core_mthd_head = { { 0x20a4, 0x6820a4 }, { 0x20a8, 0x6820a8 }, { 0x20ac, 0x6820ac }, + { 0x2180, 0x682180 }, + { 0x2184, 0x682184 }, { 0x218c, 0x68218c }, { 0x2194, 0x682194 }, { 0x2198, 0x682198 }, -- 2.29.2

1 0

[PATCH 3/5] drm/nouveau/kms/nv140-: Use hard-coded wndws or core channel for CRC channel
by Lyude Paul 19 Jan '21

19 Jan '21

Originally it was assumed based on Nvidia's open-gpu-docs and testing that NVDisplay required that at least one wndw which belongs to a given head to be used as the controlling channel (NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL) in order for CRC capture to function. While this is the case on Volta, Turing actually adds the ability to instead use the core channel as the controlling channel. For Turing this is quite useful, as it means that we can always default to the core channel as the controlling channel and we don't need to be concerned about ensuring we have at least one wndw channel owned by a head with CRC output enabled. While Volta lacks this ability, Volta conveniently also lacks flexible wndw mapping - meaning that we can always rely on each head having four wndw channels mapped to it regardless of the atomic state. So, simply use the hard-coded wndw mappings we're guaranteed to have on Volta as the controlling channel, and use the core channel as the controlling channel for Turing+. As a result this also renders the plane ownership logic in nv50_crc_atomic_check() unnessecary, which gives us one less thing to implement when we get support for flexible wndw mapping. We also can entirely drop the wndw parameter from our set_src callbacks, and the atomic state. Cc: Martin Peres <martin.peres(a)free.fr> Cc: Jeremy Cline <jcline(a)redhat.com> Cc: Simon Ser <contact(a)emersion.fr> Signed-off-by: Lyude Paul <lyude(a)redhat.com> --- drivers/gpu/drm/nouveau/dispnv50/Kbuild | 1 + drivers/gpu/drm/nouveau/dispnv50/corec57d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/crc.c | 34 ++------- drivers/gpu/drm/nouveau/dispnv50/crc.h | 7 +- drivers/gpu/drm/nouveau/dispnv50/crc907d.c | 5 +- drivers/gpu/drm/nouveau/dispnv50/crcc37d.c | 45 +++--------- drivers/gpu/drm/nouveau/dispnv50/crcc37d.h | 40 +++++++++++ drivers/gpu/drm/nouveau/dispnv50/crcc57d.c | 58 ++++++++++++++++ .../drm/nouveau/include/nvhw/class/clc57d.h | 69 +++++++++++++++++++ 9 files changed, 187 insertions(+), 74 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/dispnv50/crcc37d.h create mode 100644 drivers/gpu/drm/nouveau/dispnv50/crcc57d.c diff --git a/drivers/gpu/drm/nouveau/dispnv50/Kbuild b/drivers/gpu/drm/nouveau/dispnv50/Kbuild index 4488e1c061b3..28be2912ff74 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/Kbuild +++ b/drivers/gpu/drm/nouveau/dispnv50/Kbuild @@ -13,6 +13,7 @@ nouveau-y += dispnv50/corec57d.o nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crc.o nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crc907d.o nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crcc37d.o +nouveau-$(CONFIG_DEBUG_FS) += dispnv50/crcc57d.o nouveau-y += dispnv50/dac507d.o nouveau-y += dispnv50/dac907d.o diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c index 75876546eac1..53b1e2a569c1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c @@ -69,7 +69,7 @@ corec57d = { .head = &headc57d, .sor = &sorc37d, #if IS_ENABLED(CONFIG_DEBUG_FS) - .crc = &crcc37d, + .crc = &crcc57d, #endif }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.c b/drivers/gpu/drm/nouveau/dispnv50/crc.c index ef942248345c..49eb8e9fef22 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.c @@ -351,8 +351,6 @@ int nv50_crc_atomic_check_head(struct nv50_head *head, struct nv50_head_atom *armh) { struct nv50_atom *atom = nv50_atom(asyh->state.state); - struct drm_device *dev = head->base.base.dev; - struct nv50_disp *disp = nv50_disp(dev); bool changed = armh->crc.src != asyh->crc.src; if (!armh->crc.src && !asyh->crc.src) { @@ -361,30 +359,7 @@ int nv50_crc_atomic_check_head(struct nv50_head *head, return 0; } - /* While we don't care about entry tags, Volta+ hw always needs the - * controlling wndw channel programmed to a wndw that's owned by our - * head - */ - if (asyh->crc.src && disp->disp->object.oclass >= GV100_DISP && - !(BIT(asyh->crc.wndw) & asyh->wndw.owned)) { - if (!asyh->wndw.owned) { - /* TODO: once we support flexible channel ownership, - * we should write some code here to handle attempting - * to "steal" a plane: e.g. take a plane that is - * currently not-visible and owned by another head, - * and reassign it to this head. If we fail to do so, - * we shuld reject the mode outright as CRC capture - * then becomes impossible. - */ - NV_ATOMIC(nouveau_drm(dev), - "No available wndws for CRC readback\n"); - return -EINVAL; - } - asyh->crc.wndw = ffs(asyh->wndw.owned) - 1; - } - - if (drm_atomic_crtc_needs_modeset(&asyh->state) || changed || - armh->crc.wndw != asyh->crc.wndw) { + if (drm_atomic_crtc_needs_modeset(&asyh->state) || changed) { asyh->clr.crc = armh->crc.src && armh->state.active; asyh->set.crc = asyh->crc.src && asyh->state.active; if (changed) @@ -471,9 +446,8 @@ void nv50_crc_atomic_set(struct nv50_head *head, struct nouveau_encoder *outp = nv50_real_outp(nv50_head_atom_get_encoder(asyh)); - func->set_src(head, outp->or, - nv50_crc_source_type(outp, asyh->crc.src), - &crc->ctx[crc->ctx_idx], asyh->crc.wndw); + func->set_src(head, outp->or, nv50_crc_source_type(outp, asyh->crc.src), + &crc->ctx[crc->ctx_idx]); } void nv50_crc_atomic_clr(struct nv50_head *head) @@ -481,7 +455,7 @@ void nv50_crc_atomic_clr(struct nv50_head *head) const struct nv50_crc_func *func = nv50_disp(head->base.base.dev)->core->func->crc; - func->set_src(head, 0, NV50_CRC_SOURCE_TYPE_NONE, NULL, 0); + func->set_src(head, 0, NV50_CRC_SOURCE_TYPE_NONE, NULL); } static inline int diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.h b/drivers/gpu/drm/nouveau/dispnv50/crc.h index 4fce871b04c8..4823f1fde2dd 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.h +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.h @@ -45,13 +45,11 @@ struct nv50_crc_notifier_ctx { struct nv50_crc_atom { enum nv50_crc_source src; - /* Only used for gv100+ */ - u8 wndw : 4; }; struct nv50_crc_func { - int (*set_src)(struct nv50_head *, int or, enum nv50_crc_source_type, - struct nv50_crc_notifier_ctx *, u32 wndw); + int (*set_src)(struct nv50_head *, int or, enum nv50_crc_source_type type, + struct nv50_crc_notifier_ctx *ctx); int (*set_ctx)(struct nv50_head *, struct nv50_crc_notifier_ctx *); u32 (*get_entry)(struct nv50_head *, struct nv50_crc_notifier_ctx *, enum nv50_crc_source, int idx); @@ -95,6 +93,7 @@ void nv50_crc_atomic_clr(struct nv50_head *); extern const struct nv50_crc_func crc907d; extern const struct nv50_crc_func crcc37d; +extern const struct nv50_crc_func crcc57d; #else /* IS_ENABLED(CONFIG_DEBUG_FS) */ struct nv50_crc {}; diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c index 0fb0fdb9f119..0a89ae9523d4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c @@ -23,9 +23,8 @@ struct crc907d_notifier { } __packed; static int -crc907d_set_src(struct nv50_head *head, int or, - enum nv50_crc_source_type source, - struct nv50_crc_notifier_ctx *ctx, u32 wndw) +crc907d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source, + struct nv50_crc_notifier_ctx *ctx) { struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; const int i = head->base.index; diff --git a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c index 814e5bd97446..f10f6c484408 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c @@ -2,6 +2,7 @@ #include <drm/drm_crtc.h> #include "crc.h" +#include "crcc37d.h" #include "core.h" #include "disp.h" #include "head.h" @@ -10,38 +11,13 @@ #include <nvhw/class/clc37d.h> -#define CRCC37D_MAX_ENTRIES 2047 - -struct crcc37d_notifier { - u32 status; - - /* reserved */ - u32 :32; - u32 :32; - u32 :32; - u32 :32; - u32 :32; - u32 :32; - u32 :32; - - struct crcc37d_entry { - u32 status[2]; - u32 :32; /* reserved */ - u32 compositor_crc; - u32 rg_crc; - u32 output_crc[2]; - u32 :32; /* reserved */ - } entries[CRCC37D_MAX_ENTRIES]; -} __packed; - static int -crcc37d_set_src(struct nv50_head *head, int or, - enum nv50_crc_source_type source, - struct nv50_crc_notifier_ctx *ctx, u32 wndw) +crcc37d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source, + struct nv50_crc_notifier_ctx *ctx) { struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; const int i = head->base.index; - u32 crc_args = NVVAL(NVC37D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, wndw) | + u32 crc_args = NVVAL(NVC37D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, i * 4) | NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) | NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) | NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE); @@ -75,8 +51,7 @@ crcc37d_set_src(struct nv50_head *head, int or, return 0; } -static int -crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) +int crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) { struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; const int i = head->base.index; @@ -89,9 +64,8 @@ crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) return 0; } -static u32 crcc37d_get_entry(struct nv50_head *head, - struct nv50_crc_notifier_ctx *ctx, - enum nv50_crc_source source, int idx) +u32 crcc37d_get_entry(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx, + enum nv50_crc_source source, int idx) { struct crcc37d_notifier __iomem *notifier = ctx->mem.object.map.ptr; struct crcc37d_entry __iomem *entry = &notifier->entries[idx]; @@ -105,8 +79,7 @@ static u32 crcc37d_get_entry(struct nv50_head *head, return ioread32_native(crc_addr); } -static bool crcc37d_ctx_finished(struct nv50_head *head, - struct nv50_crc_notifier_ctx *ctx) +bool crcc37d_ctx_finished(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) { struct nouveau_drm *drm = nouveau_drm(head->base.base.dev); struct crcc37d_notifier __iomem *notifier = ctx->mem.object.map.ptr; @@ -148,7 +121,7 @@ const struct nv50_crc_func crcc37d = { .set_ctx = crcc37d_set_ctx, .get_entry = crcc37d_get_entry, .ctx_finished = crcc37d_ctx_finished, - .flip_threshold = CRCC37D_MAX_ENTRIES - 30, + .flip_threshold = CRCC37D_FLIP_THRESHOLD, .num_entries = CRCC37D_MAX_ENTRIES, .notifier_len = sizeof(struct crcc37d_notifier), }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.h b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.h new file mode 100644 index 000000000000..f54425530ce0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.h @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: MIT + +#ifndef __CRCC37D_H__ +#define __CRCC37D_H__ + +#include <linux/types.h> + +#include "crc.h" + +#define CRCC37D_MAX_ENTRIES 2047 +#define CRCC37D_FLIP_THRESHOLD CRCC37D_MAX_ENTRIES - 30 + +struct crcc37d_notifier { + u32 status; + + /* reserved */ + u32 :32; + u32 :32; + u32 :32; + u32 :32; + u32 :32; + u32 :32; + u32 :32; + + struct crcc37d_entry { + u32 status[2]; + u32 :32; /* reserved */ + u32 compositor_crc; + u32 rg_crc; + u32 output_crc[2]; + u32 :32; /* reserved */ + } entries[CRCC37D_MAX_ENTRIES]; +} __packed; + +int crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx); +u32 crcc37d_get_entry(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx, + enum nv50_crc_source source, int idx); +bool crcc37d_ctx_finished(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx); + +#endif /* !__CRCC37D_H__ */ diff --git a/drivers/gpu/drm/nouveau/dispnv50/crcc57d.c b/drivers/gpu/drm/nouveau/dispnv50/crcc57d.c new file mode 100644 index 000000000000..cc0130e3d496 --- /dev/null +++ b/drivers/gpu/drm/nouveau/dispnv50/crcc57d.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: MIT + +#include "crc.h" +#include "crcc37d.h" +#include "core.h" +#include "disp.h" +#include "head.h" + +#include <nvif/pushc37b.h> + +#include <nvhw/class/clc57d.h> + +static int crcc57d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source, + struct nv50_crc_notifier_ctx *ctx) +{ + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | + NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) | + NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) | + NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE); + int ret; + + switch (source) { + case NV50_CRC_SOURCE_TYPE_SOR: + crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or)); + break; + case NV50_CRC_SOURCE_TYPE_SF: + crc_args |= NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF); + break; + default: + break; + } + + ret = PUSH_WAIT(push, 4); + if (ret) + return ret; + + if (source) { + PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle); + PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), crc_args); + } else { + PUSH_MTHD(push, NVC57D, HEAD_SET_CRC_CONTROL(i), 0); + PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_CRC(i), 0); + } + + return 0; +} + +const struct nv50_crc_func crcc57d = { + .set_src = crcc57d_set_src, + .set_ctx = crcc37d_set_ctx, + .get_entry = crcc37d_get_entry, + .ctx_finished = crcc37d_ctx_finished, + .flip_threshold = CRCC37D_FLIP_THRESHOLD, + .num_entries = CRCC37D_MAX_ENTRIES, + .notifier_len = sizeof(struct crcc37d_notifier), +}; diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h index d83ac815e06c..d4bad2da3e56 100644 --- a/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h @@ -265,6 +265,75 @@ #define NVC57D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) #define NVC57D_HEAD_SET_RASTER_BLANK_START_X 14:0 #define NVC57D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC57D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 5:0 +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_0 (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_1 (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_2 (0x00000002) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_3 (0x00000003) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_4 (0x00000004) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_5 (0x00000005) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_6 (0x00000006) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_7 (0x00000007) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_8 (0x00000008) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_9 (0x00000009) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_10 (0x0000000A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_11 (0x0000000B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_12 (0x0000000C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_13 (0x0000000D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_14 (0x0000000E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_15 (0x0000000F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_16 (0x00000010) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_17 (0x00000011) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_18 (0x00000012) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_19 (0x00000013) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_20 (0x00000014) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_21 (0x00000015) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_22 (0x00000016) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_23 (0x00000017) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_24 (0x00000018) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_25 (0x00000019) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_26 (0x0000001A) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_27 (0x0000001B) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_28 (0x0000001C) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_29 (0x0000001D) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_30 (0x0000001E) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_WIN_31 (0x0000001F) +#define NVC57D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000020) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC57D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) #define NVC57D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) #define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 #define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) -- 2.29.2

1 0

[PATCH 2/5] drm/nouveau/kms/nv50-: Check vbl count after CRC context flip
by Lyude Paul 19 Jan '21

19 Jan '21

While I haven't seen us take too long in nv50_crc_ctx_flip_work() outside of users with kernel logging on a serial port, it probably would be a good idea to check how long we take just in case we need to go faster in the future. Cc: Martin Peres <martin.peres(a)free.fr> Cc: Jeremy Cline <jcline(a)redhat.com> Cc: Simon Ser <contact(a)emersion.fr> Signed-off-by: Lyude Paul <lyude(a)redhat.com> --- drivers/gpu/drm/nouveau/dispnv50/crc.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.c b/drivers/gpu/drm/nouveau/dispnv50/crc.c index 3c50b29a37ff..ef942248345c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.c @@ -86,6 +86,8 @@ static void nv50_crc_ctx_flip_work(struct kthread_work *base) struct drm_crtc *crtc = &head->base.base; struct drm_device *dev = crtc->dev; struct nv50_disp *disp = nv50_disp(dev); + const uint64_t start_vbl = drm_crtc_vblank_count(crtc); + uint64_t end_vbl; u8 new_idx = crc->ctx_idx ^ 1; /* @@ -94,9 +96,7 @@ static void nv50_crc_ctx_flip_work(struct kthread_work *base) */ if (!mutex_trylock(&disp->mutex)) { drm_dbg_kms(dev, "Lock contended, delaying CRC ctx flip for %s\n", crtc->name); - drm_vblank_work_schedule(work, - drm_crtc_vblank_count(crtc) + 1, - true); + drm_vblank_work_schedule(work, start_vbl + 1, true); return; } @@ -107,6 +107,12 @@ static void nv50_crc_ctx_flip_work(struct kthread_work *base) nv50_crc_program_ctx(head, &crc->ctx[new_idx]); mutex_unlock(&disp->mutex); + end_vbl = drm_crtc_vblank_count(crtc); + if (unlikely(end_vbl != start_vbl)) + NV_ERROR(nouveau_drm(dev), + "Failed to flip CRC context on %s on time (%llu > %llu)\n", + crtc->name, end_vbl, start_vbl); + spin_lock_irq(&crc->lock); crc->ctx_changed = true; spin_unlock_irq(&crc->lock); -- 2.29.2

1 0

[Bug 211263] New: amdgpu: navi (RX 5500 XT) high power consumption while idling on 75Hz display
by bugzilla-daemon＠bugzilla.kernel.org 18 Jan '21

18 Jan '21

https://bugzilla.kernel.org/show_bug.cgi?id=211263 Bug ID: 211263 Summary: amdgpu: navi (RX 5500 XT) high power consumption while idling on 75Hz display Product: Drivers Version: 2.5 Kernel Version: 5.10.7 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: contato-myghi63(a)protonmail.com Regression: No Created attachment 294731 --> https://bugzilla.kernel.org/attachment.cgi?id=294731&action=edit corectrl monitoring at 60hz and 75hz Overview: My RX 5500XT (GV-R55XTOC-8GD) consumes about 15W on idle if my monitor (24MK430) is on 75Hz, and just 3W on 60Hz. This did never happened before 5.10 kernels. Any older kernel consumes 3W even on 75Hz, same hardware, same configurations. Steps to reproduce: Install any distro with 5.10 kernel on a system that have high refresh rate display and AMD NAVI GPU. Actual results: High GPU power consumption while idling, GPU heating and fans spinning up while doing nothing on the computer. Expected results: Low power consumption and low GPU heat. Operational System: Arch Linux (latest packages avaliable from the repository) Additional Information: Here's my tlp configuration (keep in mind: that same configuration was applied on kernel 5.9.14 and 5.4.90, both working properly with 3W at 75Hz): RADEON_POWER_PROFILE_ON_AC=high RADEON_DPM_PERF_LEVEL_ON_AC=auto RADEON_DPM_STATE_ON_AC=performance -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

1 2

[PATCH] drm/msm/dsi: Correct io_start for MSM8994 (20nm PHY)
by Konrad Dybcio 18 Jan '21

18 Jan '21

The previous registers were *almost* correct, but instead of PHYs, they were pointing at DSI PLLs, resulting in the PHY id autodetection failing miserably. Fixes: dcefc117cc19 ("drm/msm/dsi: Add support for msm8x94") Signed-off-by: Konrad Dybcio <konrad.dybcio(a)somainline.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c index 1afb7c579dbb..eca86bf448f7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c @@ -139,7 +139,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = { .disable = dsi_20nm_phy_disable, .init = msm_dsi_phy_init_common, }, - .io_start = { 0xfd998300, 0xfd9a0300 }, + .io_start = { 0xfd998500, 0xfd9a0500 }, .num_dsi_phy = 2, }; -- 2.29.2

1 0

[PATCH v3 0/8] drm: Move struct drm_device.pdev to legacy
by Thomas Zimmermann 18 Jan '21

18 Jan '21

I merged many of the patches that were ready in v2 into drm-misc-next. In v3 remain only patches that need an r-b/a-b (i915/gt/gvt) or required a change from v2. The pdev field in struct drm_device points to a PCI device structure and goes back to UMS-only days when all DRM drivers were for PCI devices. Meanwhile we also support USB, SPI and platform devices. Each of those uses the generic device stored in struct drm_device.dev. To reduce duplication and remove the special case of PCI, this patchset converts all modesetting drivers from pdev to dev and makes pdev a field for legacy UMS drivers. For PCI devices, the pointer in struct drm_device.dev can be upcasted to struct pci_device; or tested for PCI with dev_is_pci(). In several places the code can use the dev field directly. After converting all drivers and the DRM core, the pdev fields becomes only relevant for legacy drivers. In a later patchset, we may want to convert these as well and remove pdev entirely. v3: * fix one pdev reference in nouveau (Jeremy) * rebases v2: * move whitespace fixes into separate patches (Alex, Sam) * move i915 gt/ and gvt/ changes into separate patches (Joonas) Thomas Zimmermann (8): drm/amdgpu: Fix trailing whitespaces drm/amdgpu: Remove references to struct drm_device.pdev drm/hibmc: Remove references to struct drm_device.pdev drm/i915: Remove references to struct drm_device.pdev drm/i915/gt: Remove references to struct drm_device.pdev drm/i915/gvt: Remove references to struct drm_device.pdev drm/nouveau: Remove references to struct drm_device.pdev drm: Upcast struct drm_device.dev to struct pci_device; replace pdev drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 23 ++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 10 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 +-- drivers/gpu/drm/drm_agpsupport.c | 9 ++- drivers/gpu/drm/drm_bufs.c | 4 +- drivers/gpu/drm/drm_edid.c | 7 ++- drivers/gpu/drm/drm_irq.c | 12 ++-- drivers/gpu/drm/drm_pci.c | 26 ++++---- drivers/gpu/drm/drm_vm.c | 2 +- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 13 ++-- .../gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c | 2 +- drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c | 61 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_bios.c | 2 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++--- drivers/gpu/drm/i915/display/intel_csr.c | 2 +- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 2 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +- .../gpu/drm/i915/display/intel_lpe_audio.c | 5 +- drivers/gpu/drm/i915/display/intel_opregion.c | 6 +- drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 4 +- drivers/gpu/drm/i915/display/intel_quirks.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/display/intel_vga.c | 8 +-- drivers/gpu/drm/i915/gem/i915_gem_phys.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 10 +-- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +- drivers/gpu/drm/i915/gt/intel_reset.c | 6 +- drivers/gpu/drm/i915/gvt/cfg_space.c | 5 +- drivers/gpu/drm/i915/gvt/firmware.c | 10 +-- drivers/gpu/drm/i915/gvt/gtt.c | 12 ++-- drivers/gpu/drm/i915/gvt/gvt.c | 6 +- drivers/gpu/drm/i915/gvt/kvmgt.c | 4 +- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.c | 20 +++--- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +- drivers/gpu/drm/i915/i915_getparam.c | 5 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_irq.c | 6 +- drivers/gpu/drm/i915/i915_pmu.c | 2 +- drivers/gpu/drm/i915/i915_suspend.c | 4 +- drivers/gpu/drm/i915/i915_switcheroo.c | 4 +- drivers/gpu/drm/i915/i915_vgpu.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_region_lmem.c | 8 +-- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 4 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 1 - drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/arb.c | 12 ++-- drivers/gpu/drm/nouveau/dispnv04/dfp.c | 5 +- drivers/gpu/drm/nouveau/dispnv04/disp.h | 14 +++-- drivers/gpu/drm/nouveau/dispnv04/hw.c | 10 +-- drivers/gpu/drm/nouveau/nouveau_abi16.c | 7 ++- drivers/gpu/drm/nouveau/nouveau_acpi.c | 2 +- drivers/gpu/drm/nouveau/nouveau_bios.c | 11 +++- drivers/gpu/drm/nouveau/nouveau_connector.c | 10 +-- drivers/gpu/drm/nouveau/nouveau_drm.c | 5 +- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 6 +- drivers/gpu/drm/nouveau/nouveau_vga.c | 20 +++--- include/drm/drm_device.h | 12 +++- 70 files changed, 296 insertions(+), 198 deletions(-) create mode 100644 drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c -- 2.29.2

5 18

Re: Change eats memory on my server
by Thomas Zimmermann 18 Jan '21

18 Jan '21

(cc'ing dri-devel) Hi Am 14.01.21 um 16:15 schrieb Eli Cohen: > Hi Thomas, > > After long bisecting I found that this patch, > > commit 1086db71a1dbbfb32ffb42cf0d540b69956f951e > Author: Thomas Zimmermann <tzimmermann(a)suse.de> > Date: Tue Nov 3 10:30:06 2020 +0100 > > drm/vram-helper: Remove invariant parameters from internal kmap function > > is the offending patch causing the kernel to eat my server memory. It > will eat all 24 GB of ram after around 7 hours. Thanks for reporting. It's a bit strange that this commit shows up, because there's nothing that should produce a memory leak. Could you please double-check that 3fb91f56aea4 ("drm/udl: Retrieve USB device from struct drm_device.dev") works correctly and that 823efa922102 ("drm/cma-helper: Remove empty drm_gem_cma_prime_vunmap()") is broken? For one of the broken commits, could you please send us the output of dmesg | grep -i drm after most of the memory got leaked? Best regards Thomas > > It's a a super micro server. The output of dmidecode is below: > > > # dmidecode 3.2 > Getting SMBIOS data from sysfs. > SMBIOS 3.1.1 present. > Table at 0x6F01B000. > > Handle 0x0000, DMI type 0, 26 bytes > BIOS Information > Vendor: American Megatrends Inc. > Version: 2.0 > Release Date: 11/30/2017 > Address: 0xF0000 > Runtime Size: 64 kB > ROM Size: 32 MB > Characteristics: > PCI is supported > BIOS is upgradeable > BIOS shadowing is allowed > Boot from CD is supported > Selectable boot is supported > BIOS ROM is socketed > EDD is supported > 5.25"/1.2 MB floppy services are supported (int 13h) > 3.5"/720 kB floppy services are supported (int 13h) > 3.5"/2.88 MB floppy services are supported (int 13h) > Print screen service is supported (int 5h) > Serial services are supported (int 14h) > Printer services are supported (int 17h) > ACPI is supported > USB legacy is supported > BIOS boot specification is supported > Targeted content distribution is supported > UEFI is supported > BIOS Revision: 5.12 > > Handle 0x0001, DMI type 1, 27 bytes > System Information > Manufacturer: Supermicro > Product Name: Super Server > Version: 0123456789 > Serial Number: 0123456789 > UUID: 00000000-0000-0000-0000-0cc47af973ca > Wake-up Type: Power Switch > SKU Number: To be filled by O.E.M. > Family: To be filled by O.E.M. > > Handle 0x0002, DMI type 2, 15 bytes > Base Board Information > Manufacturer: Supermicro > Product Name: X11DPT-B > Version: 1.02 > Serial Number: HM179S003332 > Asset Tag: To be filled by O.E.M. > Features: > Board is a hosting board > Board is replaceable > Location In Chassis: To be filled by O.E.M. > Chassis Handle: 0x0003 > Type: Motherboard > Contained Object Handles: 0 > > Handle 0x0003, DMI type 3, 22 bytes > Chassis Information > Manufacturer: Supermicro > Type: Main Server Chassis > Lock: Not Present > Version: 0123456789 > Serial Number: 0123456789 > Asset Tag: To be filled by O.E.M. > Boot-up State: Safe > Power Supply State: Safe > Thermal State: Safe > Security Status: None > OEM Information: 0x00000000 > Height: Unspecified > Number Of Power Cords: 1 > Contained Elements: 0 > SKU Number: To be filled by O.E.M. > > Handle 0x0004, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: JVGA1 > Internal Connector Type: None > External Reference Designator: VGA > External Connector Type: DB-15 female > Port Type: Video Port > > Handle 0x0005, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: JLAN1 > Internal Connector Type: None > External Reference Designator: IPMI_LAN > External Connector Type: RJ-45 > Port Type: Network Port > > Handle 0x0006, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: JUSB1 > Internal Connector Type: None > External Reference Designator: USB0/1(3.0) > External Connector Type: Access Bus (USB) > Port Type: USB > > Handle 0x0007, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: TPM/PORT80 > Internal Connector Type: Other > External Reference Designator: Not Specified > External Connector Type: None > Port Type: Other > > Handle 0x0008, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: FAN3 > Internal Connector Type: Other > External Reference Designator: Not Specified > External Connector Type: None > Port Type: Other > > Handle 0x0009, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: FAN4 > Internal Connector Type: Other > External Reference Designator: Not Specified > External Connector Type: None > Port Type: Other > > Handle 0x000A, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: JCOM1 - COM1 > Internal Connector Type: Other > External Reference Designator: Not Specified > External Connector Type: None > Port Type: Other > > Handle 0x000B, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: I-SATA6 > Internal Connector Type: Other > External Reference Designator: Not Specified > External Connector Type: None > Port Type: Other > > Handle 0x000C, DMI type 8, 9 bytes > Port Connector Information > Internal Reference Designator: JSD1 - SATA PWR > Internal Connector Type: Other > External Reference Designator: Not Specified > External Connector Type: None > Port Type: Other > > Handle 0x000D, DMI type 9, 17 bytes > System Slot Information > Designation: CPU1 SLOT1 PCI-E 3.0 X16E 3.0 X16 > Type: x16 PCI Express 3 x16 > Current Usage: In Use > Length: Long > ID: 1 > Characteristics: > 3.3 V is provided > Opening is shared > PME signal is supported > Bus Address: 0000:3b:00.0 > > Handle 0x000E, DMI type 9, 17 bytes > System Slot Information > Designation: CPU1 SIOM PCI-E 3.0 X16 > Type: x16 PCI Express 3 x16 > Current Usage: In Use > Length: Short > ID: 1 > Characteristics: > 3.3 V is provided > Opening is shared > PME signal is supported > Bus Address: 0000:18:00.0 > > Handle 0x000F, DMI type 9, 17 bytes > System Slot Information > Designation: CPU2 RSC-P-6 PCI-E 3.0 X16 3.0 X8 > Type: x16 PCI Express 3 x16 > Current Usage: Available > Length: Short > ID: 1 > Characteristics: > 3.3 V is provided > Opening is shared > PME signal is supported > Bus Address: 0000:af:00.0 > > Handle 0x0011, DMI type 11, 5 bytes > OEM Strings > String 1: Intel Skylake/Lewisburg/Purley > String 2: Supermicro motherboard-X11 Series > > Handle 0x0012, DMI type 32, 20 bytes > System Boot Information > Status: No errors detected > > Handle 0x0013, DMI type 39, 22 bytes > System Power Supply > Power Unit Group: 1 > Location: PSU1 > Name: PWS-2K22A-1R > Manufacturer: SUPERMICRO > Serial Number: P2K22CH46JT0157 > Asset Tag: N/A > Model Part Number: PWS-2K22A-1R > Revision: 1.3 > Max Power Capacity: 2200 W > Status: Present, OK > Type: Switching > Input Voltage Range Switching: Auto-switch > Plugged: Yes > Hot Replaceable: No > > Handle 0x0014, DMI type 39, 22 bytes > System Power Supply > Power Unit Group: 2 > Location: PSU2 > Name: PWS-2K22A-1R > Manufacturer: SUPERMICRO > Serial Number: P2K22CH46JT0155 > Asset Tag: N/A > Model Part Number: PWS-2K22A-1R > Revision: 1.3 > Max Power Capacity: 2200 W > Status: Present, OK > Type: Switching > Input Voltage Range Switching: Auto-switch > Plugged: Yes > Hot Replaceable: No > > Handle 0x0015, DMI type 41, 11 bytes > Onboard Device > Reference Designation: ASPEED Video AST2500 > Type: Video > Status: Enabled > Type Instance: 1 > Bus Address: 0000:03:00.0 > > Handle 0x0016, DMI type 38, 18 bytes > IPMI Device Information > Interface Type: KCS (Keyboard Control Style) > Specification Version: 2.0 > I2C Slave Address: 0x10 > NV Storage Device: Not Present > Base Address: 0x0000000000000CA2 (I/O) > Register Spacing: Successive Byte Boundaries > > Handle 0x0017, DMI type 42, 12 bytes > Management Controller Host Interface > Interface Type: KCS: Keyboard Controller Style > > Handle 0x001C, DMI type 15, 73 bytes > System Event Log > Area Length: 65535 bytes > Header Start Offset: 0x0000 > Header Length: 16 bytes > Data Start Offset: 0x0010 > Access Method: Memory-mapped physical 32-bit address > Access Address: 0xFF110000 > Status: Valid, Not Full > Change Token: 0x00000001 > Header Format: Type 1 > Supported Log Type Descriptors: 25 > Descriptor 1: Single-bit ECC memory error > Data Format 1: Multiple-event handle > Descriptor 2: Multi-bit ECC memory error > Data Format 2: Multiple-event handle > Descriptor 3: Parity memory error > Data Format 3: None > Descriptor 4: Bus timeout > Data Format 4: None > Descriptor 5: I/O channel block > Data Format 5: None > Descriptor 6: Software NMI > Data Format 6: None > Descriptor 7: POST memory resize > Data Format 7: None > Descriptor 8: POST error > Data Format 8: POST results bitmap > Descriptor 9: PCI parity error > Data Format 9: Multiple-event handle > Descriptor 10: PCI system error > Data Format 10: Multiple-event handle > Descriptor 11: CPU failure > Data Format 11: None > Descriptor 12: EISA failsafe timer timeout > Data Format 12: None > Descriptor 13: Correctable memory log disabled > Data Format 13: None > Descriptor 14: Logging disabled > Data Format 14: None > Descriptor 15: System limit exceeded > Data Format 15: None > Descriptor 16: Asynchronous hardware timer expired > Data Format 16: None > Descriptor 17: System configuration information > Data Format 17: None > Descriptor 18: Hard disk information > Data Format 18: None > Descriptor 19: System reconfigured > Data Format 19: None > Descriptor 20: Uncorrectable CPU-complex error > Data Format 20: None > Descriptor 21: Log area reset/cleared > Data Format 21: None > Descriptor 22: System boot > Data Format 22: None > Descriptor 23: End of log > Data Format 23: None > Descriptor 24: OEM-specific > Data Format 24: OEM-specific > Descriptor 25: OEM-specific > Data Format 25: OEM-specific > > Handle 0x001D, DMI type 16, 23 bytes > Physical Memory Array > Location: System Board Or Motherboard > Use: System Memory > Error Correction Type: Single-bit ECC > Maximum Capacity: 2304 GB > Error Information Handle: Not Provided > Number Of Devices: 6 > > Handle 0x001E, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x001D > Error Information Handle: Not Provided > Total Width: 72 bits > Data Width: 64 bits > Size: 8 GB > Form Factor: DIMM > Set: None > Locator: P1-DIMMA1 > Bank Locator: P0_Node0_Channel0_Dimm0 > Type: DDR4 > Type Detail: Synchronous > Speed: 2400 MT/s > Manufacturer: Micron Technology > Serial Number: 181E11CB > Asset Tag: P1-DIMMA1_AssetTag (date:17/31) > Part Number: 9ASF1G72PZ-2G3B1 > Rank: 1 > Configured Memory Speed: 2400 MT/s > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x001F, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x001D > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMA2 > Bank Locator: P0_Node0_Channel0_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0020, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x001D > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMB1 > Bank Locator: P0_Node0_Channel1_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0021, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x001D > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMB2 > Bank Locator: P0_Node0_Channel1_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0022, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x001D > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMC1 > Bank Locator: P0_Node0_Channel2_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0023, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x001D > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMC2 > Bank Locator: P0_Node0_Channel2_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0024, DMI type 16, 23 bytes > Physical Memory Array > Location: System Board Or Motherboard > Use: System Memory > Error Correction Type: Single-bit ECC > Maximum Capacity: 2304 GB > Error Information Handle: Not Provided > Number Of Devices: 6 > > Handle 0x0025, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0024 > Error Information Handle: Not Provided > Total Width: 72 bits > Data Width: 64 bits > Size: 8 GB > Form Factor: DIMM > Set: None > Locator: P1-DIMMD1 > Bank Locator: P0_Node1_Channel0_Dimm0 > Type: DDR4 > Type Detail: Synchronous > Speed: 2400 MT/s > Manufacturer: Micron Technology > Serial Number: 181E129C > Asset Tag: P1-DIMMD1_AssetTag (date:17/31) > Part Number: 9ASF1G72PZ-2G3B1 > Rank: 1 > Configured Memory Speed: 2400 MT/s > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0026, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0024 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMD2 > Bank Locator: P0_Node1_Channel0_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0027, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0024 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMME1 > Bank Locator: P0_Node1_Channel1_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0028, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0024 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMME2 > Bank Locator: P0_Node1_Channel1_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0029, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0024 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMF1 > Bank Locator: P0_Node1_Channel2_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x002A, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0024 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P1-DIMMF2 > Bank Locator: P0_Node1_Channel2_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x002B, DMI type 16, 23 bytes > Physical Memory Array > Location: System Board Or Motherboard > Use: System Memory > Error Correction Type: Single-bit ECC > Maximum Capacity: 2304 GB > Error Information Handle: Not Provided > Number Of Devices: 6 > > Handle 0x002C, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x002B > Error Information Handle: Not Provided > Total Width: 72 bits > Data Width: 64 bits > Size: 8 GB > Form Factor: DIMM > Set: None > Locator: P2-DIMMA1 > Bank Locator: P1_Node0_Channel0_Dimm0 > Type: DDR4 > Type Detail: Synchronous > Speed: 2400 MT/s > Manufacturer: Micron Technology > Serial Number: 181E1283 > Asset Tag: P2-DIMMA1_AssetTag (date:17/31) > Part Number: 9ASF1G72PZ-2G3B1 > Rank: 1 > Configured Memory Speed: 2400 MT/s > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x002D, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x002B > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMA2 > Bank Locator: P1_Node0_Channel0_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x002E, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x002B > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMB1 > Bank Locator: P1_Node0_Channel1_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x002F, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x002B > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMB2 > Bank Locator: P1_Node0_Channel1_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0030, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x002B > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMC1 > Bank Locator: P1_Node0_Channel2_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0031, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x002B > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMC2 > Bank Locator: P1_Node0_Channel2_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0032, DMI type 16, 23 bytes > Physical Memory Array > Location: System Board Or Motherboard > Use: System Memory > Error Correction Type: Single-bit ECC > Maximum Capacity: 2304 GB > Error Information Handle: Not Provided > Number Of Devices: 6 > > Handle 0x0033, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0032 > Error Information Handle: Not Provided > Total Width: 72 bits > Data Width: 64 bits > Size: 8 GB > Form Factor: DIMM > Set: None > Locator: P2-DIMMD1 > Bank Locator: P1_Node1_Channel0_Dimm0 > Type: DDR4 > Type Detail: Synchronous > Speed: 2400 MT/s > Manufacturer: Micron Technology > Serial Number: 181E122C > Asset Tag: P2-DIMMD1_AssetTag (date:17/31) > Part Number: 9ASF1G72PZ-2G3B1 > Rank: 1 > Configured Memory Speed: 2400 MT/s > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0034, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0032 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMD2 > Bank Locator: P1_Node1_Channel0_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0035, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0032 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMME1 > Bank Locator: P1_Node1_Channel1_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0036, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0032 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMME2 > Bank Locator: P1_Node1_Channel1_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0037, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0032 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMF1 > Bank Locator: P1_Node1_Channel2_Dimm0 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0038, DMI type 17, 40 bytes > Memory Device > Array Handle: 0x0032 > Error Information Handle: Not Provided > Total Width: Unknown > Data Width: Unknown > Size: No Module Installed > Form Factor: DIMM > Set: None > Locator: P2-DIMMF2 > Bank Locator: P1_Node1_Channel2_Dimm1 > Type: Unknown > Type Detail: Unknown > Speed: Unknown > Manufacturer: NO DIMM > Serial Number: NO DIMM > Asset Tag: NO DIMM > Part Number: NO DIMM > Rank: Unknown > Configured Memory Speed: Unknown > Minimum Voltage: 1.2 V > Maximum Voltage: 1.2 V > Configured Voltage: 1.2 V > > Handle 0x0039, DMI type 19, 31 bytes > Memory Array Mapped Address > Starting Address: 0x00000000000 > Ending Address: 0x001FFFFFFFF > Range Size: 8 GB > Physical Array Handle: 0x001D > Partition Width: 1 > > Handle 0x003A, DMI type 20, 35 bytes > Memory Device Mapped Address > Starting Address: 0x00000000000 > Ending Address: 0x001FFFFFFFF > Range Size: 8 GB > Physical Device Handle: 0x001E > Memory Array Mapped Address Handle: 0x0039 > Partition Row Position: 1 > Interleave Position: 1 > Interleaved Data Depth: 1 > > Handle 0x003B, DMI type 19, 31 bytes > Memory Array Mapped Address > Starting Address: 0x00200000000 > Ending Address: 0x003FFFFFFFF > Range Size: 8 GB > Physical Array Handle: 0x0024 > Partition Width: 1 > > Handle 0x003C, DMI type 20, 35 bytes > Memory Device Mapped Address > Starting Address: 0x00000000000 > Ending Address: 0x001FFFFFFFF > Range Size: 8 GB > Physical Device Handle: 0x0025 > Memory Array Mapped Address Handle: 0x003B > Partition Row Position: 1 > Interleave Position: 1 > Interleaved Data Depth: 1 > > Handle 0x003D, DMI type 19, 31 bytes > Memory Array Mapped Address > Starting Address: 0x00400000000 > Ending Address: 0x005FFFFFFFF > Range Size: 8 GB > Physical Array Handle: 0x002B > Partition Width: 1 > > Handle 0x003E, DMI type 20, 35 bytes > Memory Device Mapped Address > Starting Address: 0x00000000000 > Ending Address: 0x001FFFFFFFF > Range Size: 8 GB > Physical Device Handle: 0x002C > Memory Array Mapped Address Handle: 0x003D > Partition Row Position: 1 > Interleave Position: 1 > Interleaved Data Depth: 1 > > Handle 0x003F, DMI type 19, 31 bytes > Memory Array Mapped Address > Starting Address: 0x00600000000 > Ending Address: 0x007FFFFFFFF > Range Size: 8 GB > Physical Array Handle: 0x0032 > Partition Width: 1 > > Handle 0x0040, DMI type 20, 35 bytes > Memory Device Mapped Address > Starting Address: 0x00000000000 > Ending Address: 0x001FFFFFFFF > Range Size: 8 GB > Physical Device Handle: 0x0033 > Memory Array Mapped Address Handle: 0x003F > Partition Row Position: 1 > Interleave Position: 1 > Interleaved Data Depth: 1 > > Handle 0x0041, DMI type 7, 19 bytes > Cache Information > Socket Designation: L1 Cache > Configuration: Enabled, Not Socketed, Level 1 > Operational Mode: Write Back > Location: Internal > Installed Size: 512 kB > Maximum Size: 512 kB > Supported SRAM Types: > Synchronous > Installed SRAM Type: Synchronous > Speed: Unknown > Error Correction Type: Single-bit ECC > System Type: Instruction > Associativity: 8-way Set-associative > > Handle 0x0042, DMI type 7, 19 bytes > Cache Information > Socket Designation: L2 Cache > Configuration: Enabled, Not Socketed, Level 2 > Operational Mode: Varies With Memory Address > Location: Internal > Installed Size: 8 MB > Maximum Size: 8 MB > Supported SRAM Types: > Synchronous > Installed SRAM Type: Synchronous > Speed: Unknown > Error Correction Type: Single-bit ECC > System Type: Unified > Associativity: 16-way Set-associative > > Handle 0x0043, DMI type 7, 19 bytes > Cache Information > Socket Designation: L3 Cache > Configuration: Enabled, Not Socketed, Level 3 > Operational Mode: Varies With Memory Address > Location: Internal > Installed Size: 11 MB > Maximum Size: 11 MB > Supported SRAM Types: > Synchronous > Installed SRAM Type: Synchronous > Speed: Unknown > Error Correction Type: Single-bit ECC > System Type: Unified > Associativity: Fully Associative > > Handle 0x0044, DMI type 4, 48 bytes > Processor Information > Socket Designation: CPU1 > Type: Central Processor > Family: Xeon > Manufacturer: Intel(R) Corporation > ID: 54 06 05 00 FF FB EB BF > Signature: Type 0, Family 6, Model 85, Stepping 4 > Flags: > FPU (Floating-point unit on-chip) > VME (Virtual mode extension) > DE (Debugging extension) > PSE (Page size extension) > TSC (Time stamp counter) > MSR (Model specific registers) > PAE (Physical address extension) > MCE (Machine check exception) > CX8 (CMPXCHG8 instruction supported) > APIC (On-chip APIC hardware supported) > SEP (Fast system call) > MTRR (Memory type range registers) > PGE (Page global enable) > MCA (Machine check architecture) > CMOV (Conditional move instruction supported) > PAT (Page attribute table) > PSE-36 (36-bit page size extension) > CLFSH (CLFLUSH instruction supported) > DS (Debug store) > ACPI (ACPI supported) > MMX (MMX technology supported) > FXSR (FXSAVE and FXSTOR instructions supported) > SSE (Streaming SIMD extensions) > SSE2 (Streaming SIMD extensions 2) > SS (Self-snoop) > HTT (Multi-threading) > TM (Thermal monitor supported) > PBE (Pending break enabled) > Version: Intel(R) Xeon(R) Silver 4108 CPU @ 1.80GHz > Voltage: 1.6 V > External Clock: 100 MHz > Max Speed: 4000 MHz > Current Speed: 1800 MHz > Status: Populated, Enabled > Upgrade: Other > L1 Cache Handle: 0x0041 > L2 Cache Handle: 0x0042 > L3 Cache Handle: 0x0043 > Serial Number: Not Specified > Asset Tag: UNKNOWN > Part Number: Not Specified > Core Count: 8 > Core Enabled: 8 > Thread Count: 16 > Characteristics: > 64-bit capable > Multi-Core > Hardware Thread > Execute Protection > Enhanced Virtualization > Power/Performance Control > > Handle 0x0045, DMI type 7, 19 bytes > Cache Information > Socket Designation: L1 Cache > Configuration: Enabled, Not Socketed, Level 1 > Operational Mode: Write Back > Location: Internal > Installed Size: 512 kB > Maximum Size: 512 kB > Supported SRAM Types: > Synchronous > Installed SRAM Type: Synchronous > Speed: Unknown > Error Correction Type: Single-bit ECC > System Type: Instruction > Associativity: 8-way Set-associative > > Handle 0x0046, DMI type 7, 19 bytes > Cache Information > Socket Designation: L2 Cache > Configuration: Enabled, Not Socketed, Level 2 > Operational Mode: Varies With Memory Address > Location: Internal > Installed Size: 8 MB > Maximum Size: 8 MB > Supported SRAM Types: > Synchronous > Installed SRAM Type: Synchronous > Speed: Unknown > Error Correction Type: Single-bit ECC > System Type: Unified > Associativity: 16-way Set-associative > > Handle 0x0047, DMI type 7, 19 bytes > Cache Information > Socket Designation: L3 Cache > Configuration: Enabled, Not Socketed, Level 3 > Operational Mode: Varies With Memory Address > Location: Internal > Installed Size: 11 MB > Maximum Size: 11 MB > Supported SRAM Types: > Synchronous > Installed SRAM Type: Synchronous > Speed: Unknown > Error Correction Type: Single-bit ECC > System Type: Unified > Associativity: Fully Associative > > Handle 0x0048, DMI type 4, 48 bytes > Processor Information > Socket Designation: CPU2 > Type: Central Processor > Family: Xeon > Manufacturer: Intel(R) Corporation > ID: 54 06 05 00 FF FB EB BF > Signature: Type 0, Family 6, Model 85, Stepping 4 > Flags: > FPU (Floating-point unit on-chip) > VME (Virtual mode extension) > DE (Debugging extension) > PSE (Page size extension) > TSC (Time stamp counter) > MSR (Model specific registers) > PAE (Physical address extension) > MCE (Machine check exception) > CX8 (CMPXCHG8 instruction supported) > APIC (On-chip APIC hardware supported) > SEP (Fast system call) > MTRR (Memory type range registers) > PGE (Page global enable) > MCA (Machine check architecture) > CMOV (Conditional move instruction supported) > PAT (Page attribute table) > PSE-36 (36-bit page size extension) > CLFSH (CLFLUSH instruction supported) > DS (Debug store) > ACPI (ACPI supported) > MMX (MMX technology supported) > FXSR (FXSAVE and FXSTOR instructions supported) > SSE (Streaming SIMD extensions) > SSE2 (Streaming SIMD extensions 2) > SS (Self-snoop) > HTT (Multi-threading) > TM (Thermal monitor supported) > PBE (Pending break enabled) > Version: Intel(R) Xeon(R) Silver 4108 CPU @ 1.80GHz > Voltage: 1.6 V > External Clock: 100 MHz > Max Speed: 4000 MHz > Current Speed: 1800 MHz > Status: Populated, Enabled > Upgrade: Other > L1 Cache Handle: 0x0045 > L2 Cache Handle: 0x0046 > L3 Cache Handle: 0x0047 > Serial Number: Not Specified > Asset Tag: UNKNOWN > Part Number: Not Specified > Core Count: 8 > Core Enabled: 8 > Thread Count: 16 > Characteristics: > 64-bit capable > Multi-Core > Hardware Thread > Execute Protection > Enhanced Virtualization > Power/Performance Control > > Handle 0x004D, DMI type 40, 27 bytes > Additional Information 1 > > Handle 0x004E, DMI type 40, 200 bytes > Additional Information 1 > > Handle 0x004F, DMI type 40, 27 bytes > Additional Information 1 > > Handle 0x0050, DMI type 40, 27 bytes > Additional Information 1 > > Handle 0x0051, DMI type 130, 32 bytes > OEM-specific Type > Header and Data: > 82 20 51 00 01 00 20 00 00 00 04 00 00 00 00 01 > 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > Strings: > RSC-P-6 > > Handle 0x0052, DMI type 130, 32 bytes > OEM-specific Type > Header and Data: > 82 20 52 00 01 00 20 00 00 00 02 00 00 00 00 01 > 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > Strings: > BPN-ADP-12S3216N4-2UB > > Handle 0x0053, DMI type 40, 27 bytes > Additional Information 1 > > Handle 0x0054, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 54 00 06 00 00 86 80 20 20 D9 15 62 09 00 > 00 00 00 00 00 00 00 > > Handle 0x0055, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 55 00 54 00 00 00 00 00 > > Handle 0x0056, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 56 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0057, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 57 00 56 00 00 00 04 00 > > Handle 0x0058, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 58 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0059, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 59 00 58 00 00 00 04 01 > > Handle 0x005A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 5A 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x005B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 5B 00 5A 00 00 00 04 02 > > Handle 0x005C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 5C 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x005D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 5D 00 5C 00 00 00 04 03 > > Handle 0x005E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 5E 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x005F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 5F 00 5E 00 00 00 04 04 > > Handle 0x0060, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 60 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0061, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 61 00 60 00 00 00 04 05 > > Handle 0x0062, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 62 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0063, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 63 00 62 00 00 00 04 06 > > Handle 0x0064, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 64 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0065, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 65 00 64 00 00 00 04 07 > > Handle 0x0066, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 66 00 08 00 00 86 80 24 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0067, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 67 00 66 00 00 00 05 00 > > Handle 0x0068, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 68 00 08 00 00 86 80 25 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0069, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 69 00 68 00 00 00 05 02 > > Handle 0x006A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 6A 00 08 00 00 86 80 26 20 86 80 26 20 00 > 00 00 00 00 00 00 00 > > Handle 0x006B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 6B 00 6A 00 00 00 05 04 > > Handle 0x006C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 6C 00 08 00 00 86 80 14 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x006D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 6D 00 6C 00 00 00 08 00 > > Handle 0x006E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 6E 00 08 00 00 86 80 16 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x006F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 6F 00 6E 00 00 00 08 02 > > Handle 0x0070, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 70 00 06 00 00 86 80 90 A1 D9 15 62 09 01 > 00 00 00 00 00 00 00 > > Handle 0x0071, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 71 00 70 00 00 00 1C 00 > > Handle 0x0072, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 72 00 06 00 00 86 80 95 A1 D9 15 62 09 02 > 00 00 00 01 00 00 00 > > Handle 0x0073, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 73 00 72 00 00 00 1C 05 > > Handle 0x0074, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 74 00 06 00 00 03 1A 50 11 03 1A 50 11 02 > 00 00 00 01 00 00 00 > > Handle 0x0075, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 75 00 74 00 00 02 00 00 > > Handle 0x0076, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 76 00 06 06 00 86 80 30 20 D9 15 62 09 02 > 00 00 00 04 00 00 00 > > Handle 0x0077, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 77 00 76 00 00 17 00 00 > > Handle 0x0078, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 78 00 02 06 00 86 80 21 15 D9 15 12 09 02 > 00 00 00 04 00 00 00 > > Handle 0x0079, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 79 00 78 00 00 18 00 00 > > Handle 0x007A, DMI type 190, 58 bytes > OEM-specific Type > Header and Data: > BE 3A 7A 00 02 06 00 86 80 21 15 D9 15 12 09 02 > 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 > > Handle 0x007B, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 7B 00 02 06 00 86 80 21 15 D9 15 12 09 02 > 00 00 00 04 00 00 00 > > Handle 0x007C, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 7C 00 7B 00 00 18 00 01 > > Handle 0x007D, DMI type 190, 58 bytes > OEM-specific Type > Header and Data: > BE 3A 7D 00 02 06 00 86 80 21 15 D9 15 12 09 02 > 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 > > Handle 0x007E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 7E 00 08 00 00 86 80 34 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x007F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 7F 00 7E 00 00 17 05 00 > > Handle 0x0080, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 80 00 08 00 00 86 80 35 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0081, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 81 00 80 00 00 17 05 02 > > Handle 0x0082, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 82 00 08 00 00 86 80 36 20 86 80 36 20 00 > 00 00 00 00 00 00 00 > > Handle 0x0083, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 83 00 82 00 00 17 05 04 > > Handle 0x0084, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 84 00 06 01 00 86 80 30 20 D9 15 62 09 03 > 00 00 00 10 00 00 00 > > Handle 0x0085, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 85 00 84 00 00 3A 00 00 > > Handle 0x0086, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 86 00 02 01 00 B3 15 1D 10 B3 15 83 00 03 > 00 00 00 10 00 00 00 > > Handle 0x0087, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 87 00 86 00 00 3B 00 00 > > Handle 0x0088, DMI type 190, 58 bytes > OEM-specific Type > Header and Data: > BE 3A 88 00 02 01 00 B3 15 1D 10 B3 15 83 00 03 > 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 > > Handle 0x0089, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 89 00 02 01 00 B3 15 1D 10 B3 15 83 00 03 > 00 00 00 10 00 00 00 > > Handle 0x008A, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 8A 00 89 00 00 3B 00 01 > > Handle 0x008B, DMI type 190, 58 bytes > OEM-specific Type > Header and Data: > BE 3A 8B 00 02 01 00 B3 15 1D 10 B3 15 83 00 03 > 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 > > Handle 0x008C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 8C 00 08 00 00 86 80 34 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x008D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 8D 00 8C 00 00 3A 05 00 > > Handle 0x008E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 8E 00 08 00 00 86 80 35 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x008F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 8F 00 8E 00 00 3A 05 02 > > Handle 0x0090, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 90 00 08 00 00 86 80 36 20 86 80 36 20 00 > 00 00 00 00 00 00 00 > > Handle 0x0091, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 91 00 90 00 00 3A 05 04 > > Handle 0x0092, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 92 00 08 00 00 86 80 66 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0093, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 93 00 92 00 00 3A 08 00 > > Handle 0x0094, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 94 00 08 00 00 86 80 66 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0095, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 95 00 94 00 00 3A 09 00 > > Handle 0x0096, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 96 00 08 00 00 86 80 40 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0097, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 97 00 96 00 00 3A 0A 00 > > Handle 0x0098, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 98 00 08 00 00 86 80 41 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0099, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 99 00 98 00 00 3A 0A 01 > > Handle 0x009A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 9A 00 08 00 00 86 80 42 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x009B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 9B 00 9A 00 00 3A 0A 02 > > Handle 0x009C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 9C 00 08 00 00 86 80 43 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x009D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 9D 00 9C 00 00 3A 0A 03 > > Handle 0x009E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 9E 00 08 00 00 86 80 44 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x009F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 9F 00 9E 00 00 3A 0A 04 > > Handle 0x00A0, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 A0 00 08 00 00 86 80 45 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00A1, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A A1 00 A0 00 00 3A 0A 05 > > Handle 0x00A2, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 A2 00 08 00 00 86 80 46 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00A3, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A A3 00 A2 00 00 3A 0A 06 > > Handle 0x00A4, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 A4 00 08 00 00 86 80 47 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00A5, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A A5 00 A4 00 00 3A 0A 07 > > Handle 0x00A6, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 A6 00 08 00 00 86 80 48 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00A7, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A A7 00 A6 00 00 3A 0B 00 > > Handle 0x00A8, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 A8 00 08 00 00 86 80 49 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00A9, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A A9 00 A8 00 00 3A 0B 01 > > Handle 0x00AA, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 AA 00 08 00 00 86 80 4A 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00AB, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A AB 00 AA 00 00 3A 0B 02 > > Handle 0x00AC, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 AC 00 08 00 00 86 80 4B 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00AD, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A AD 00 AC 00 00 3A 0B 03 > > Handle 0x00AE, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 AE 00 08 00 00 86 80 40 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00AF, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A AF 00 AE 00 00 3A 0C 00 > > Handle 0x00B0, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 B0 00 08 00 00 86 80 41 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00B1, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A B1 00 B0 00 00 3A 0C 01 > > Handle 0x00B2, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 B2 00 08 00 00 86 80 42 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00B3, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A B3 00 B2 00 00 3A 0C 02 > > Handle 0x00B4, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 B4 00 08 00 00 86 80 43 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00B5, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A B5 00 B4 00 00 3A 0C 03 > > Handle 0x00B6, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 B6 00 08 00 00 86 80 44 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00B7, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A B7 00 B6 00 00 3A 0C 04 > > Handle 0x00B8, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 B8 00 08 00 00 86 80 45 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00B9, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A B9 00 B8 00 00 3A 0C 05 > > Handle 0x00BA, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 BA 00 08 00 00 86 80 46 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00BB, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A BB 00 BA 00 00 3A 0C 06 > > Handle 0x00BC, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 BC 00 08 00 00 86 80 47 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00BD, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A BD 00 BC 00 00 3A 0C 07 > > Handle 0x00BE, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 BE 00 08 00 00 86 80 48 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00BF, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A BF 00 BE 00 00 3A 0D 00 > > Handle 0x00C0, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 C0 00 08 00 00 86 80 49 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00C1, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A C1 00 C0 00 00 3A 0D 01 > > Handle 0x00C2, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 C2 00 08 00 00 86 80 4A 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00C3, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A C3 00 C2 00 00 3A 0D 02 > > Handle 0x00C4, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 C4 00 08 00 00 86 80 4B 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00C5, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A C5 00 C4 00 00 3A 0D 03 > > Handle 0x00C6, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 C6 00 08 00 00 86 80 34 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00C7, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A C7 00 C6 00 00 5D 05 00 > > Handle 0x00C8, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 C8 00 08 00 00 86 80 35 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00C9, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A C9 00 C8 00 00 5D 05 02 > > Handle 0x00CA, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 CA 00 08 00 00 86 80 36 20 86 80 36 20 00 > 00 00 00 00 00 00 00 > > Handle 0x00CB, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A CB 00 CA 00 00 5D 05 04 > > Handle 0x00CC, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 CC 00 11 00 00 86 80 58 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00CD, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A CD 00 CC 00 00 5D 0E 00 > > Handle 0x00CE, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 CE 00 08 00 00 86 80 59 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00CF, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A CF 00 CE 00 00 5D 0E 01 > > Handle 0x00D0, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 D0 00 11 00 00 86 80 58 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00D1, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A D1 00 D0 00 00 5D 0F 00 > > Handle 0x00D2, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 D2 00 08 00 00 86 80 59 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00D3, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A D3 00 D2 00 00 5D 0F 01 > > Handle 0x00D4, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 D4 00 11 00 00 86 80 4C 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00D5, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A D5 00 D4 00 00 5D 12 00 > > Handle 0x00D6, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 D6 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00D7, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A D7 00 D6 00 00 80 04 00 > > Handle 0x00D8, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 D8 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00D9, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A D9 00 D8 00 00 80 04 01 > > Handle 0x00DA, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 DA 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00DB, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A DB 00 DA 00 00 80 04 02 > > Handle 0x00DC, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 DC 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00DD, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A DD 00 DC 00 00 80 04 03 > > Handle 0x00DE, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 DE 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00DF, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A DF 00 DE 00 00 80 04 04 > > Handle 0x00E0, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 E0 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00E1, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A E1 00 E0 00 00 80 04 05 > > Handle 0x00E2, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 E2 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00E3, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A E3 00 E2 00 00 80 04 06 > > Handle 0x00E4, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 E4 00 08 00 00 86 80 21 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00E5, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A E5 00 E4 00 00 80 04 07 > > Handle 0x00E6, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 E6 00 08 00 00 86 80 24 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00E7, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A E7 00 E6 00 00 80 05 00 > > Handle 0x00E8, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 E8 00 08 00 00 86 80 25 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00E9, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A E9 00 E8 00 00 80 05 02 > > Handle 0x00EA, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 EA 00 08 00 00 86 80 26 20 86 80 26 20 00 > 00 00 00 00 00 00 00 > > Handle 0x00EB, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A EB 00 EA 00 00 80 05 04 > > Handle 0x00EC, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 EC 00 08 00 00 86 80 14 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00ED, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A ED 00 EC 00 00 80 08 00 > > Handle 0x00EE, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 EE 00 08 00 00 86 80 16 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00EF, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A EF 00 EE 00 00 80 08 02 > > Handle 0x00F0, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 F0 00 06 00 00 86 80 30 20 D9 15 62 09 03 > 00 00 00 08 00 00 00 > > Handle 0x00F1, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A F1 00 F0 00 00 85 00 00 > > Handle 0x00F2, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 F2 00 01 00 00 00 10 C9 00 D9 15 72 09 03 > 00 00 00 08 00 00 00 > > Handle 0x00F3, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A F3 00 F2 00 00 86 00 00 > > Handle 0x00F4, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 F4 00 08 00 00 86 80 34 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00F5, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A F5 00 F4 00 00 85 05 00 > > Handle 0x00F6, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 F6 00 08 00 00 86 80 35 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00F7, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A F7 00 F6 00 00 85 05 02 > > Handle 0x00F8, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 F8 00 08 00 00 86 80 36 20 86 80 36 20 00 > 00 00 00 00 00 00 00 > > Handle 0x00F9, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A F9 00 F8 00 00 85 05 04 > > Handle 0x00FA, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 FA 00 06 02 00 86 80 30 20 D9 15 62 09 01 > 00 00 00 00 00 00 00 > > Handle 0x00FB, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A FB 00 FA 00 00 AE 00 00 > > Handle 0x00FC, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 FC 00 08 00 00 86 80 34 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00FD, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A FD 00 FC 00 00 AE 05 00 > > Handle 0x00FE, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 FE 00 08 00 00 86 80 35 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x00FF, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A FF 00 FE 00 00 AE 05 02 > > Handle 0x0100, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 00 01 08 00 00 86 80 36 20 86 80 36 20 00 > 00 00 00 00 00 00 00 > > Handle 0x0101, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 01 01 00 01 00 AE 05 04 > > Handle 0x0102, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 02 01 08 00 00 86 80 66 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0103, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 03 01 02 01 00 AE 08 00 > > Handle 0x0104, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 04 01 08 00 00 86 80 66 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0105, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 05 01 04 01 00 AE 09 00 > > Handle 0x0106, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 06 01 08 00 00 86 80 40 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0107, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 07 01 06 01 00 AE 0A 00 > > Handle 0x0108, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 08 01 08 00 00 86 80 41 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0109, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 09 01 08 01 00 AE 0A 01 > > Handle 0x010A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 0A 01 08 00 00 86 80 42 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x010B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 0B 01 0A 01 00 AE 0A 02 > > Handle 0x010C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 0C 01 08 00 00 86 80 43 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x010D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 0D 01 0C 01 00 AE 0A 03 > > Handle 0x010E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 0E 01 08 00 00 86 80 44 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x010F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 0F 01 0E 01 00 AE 0A 04 > > Handle 0x0110, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 10 01 08 00 00 86 80 45 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0111, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 11 01 10 01 00 AE 0A 05 > > Handle 0x0112, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 12 01 08 00 00 86 80 46 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0113, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 13 01 12 01 00 AE 0A 06 > > Handle 0x0114, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 14 01 08 00 00 86 80 47 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0115, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 15 01 14 01 00 AE 0A 07 > > Handle 0x0116, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 16 01 08 00 00 86 80 48 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0117, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 17 01 16 01 00 AE 0B 00 > > Handle 0x0118, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 18 01 08 00 00 86 80 49 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0119, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 19 01 18 01 00 AE 0B 01 > > Handle 0x011A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 1A 01 08 00 00 86 80 4A 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x011B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 1B 01 1A 01 00 AE 0B 02 > > Handle 0x011C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 1C 01 08 00 00 86 80 4B 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x011D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 1D 01 1C 01 00 AE 0B 03 > > Handle 0x011E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 1E 01 08 00 00 86 80 40 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x011F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 1F 01 1E 01 00 AE 0C 00 > > Handle 0x0120, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 20 01 08 00 00 86 80 41 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0121, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 21 01 20 01 00 AE 0C 01 > > Handle 0x0122, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 22 01 08 00 00 86 80 42 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0123, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 23 01 22 01 00 AE 0C 02 > > Handle 0x0124, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 24 01 08 00 00 86 80 43 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0125, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 25 01 24 01 00 AE 0C 03 > > Handle 0x0126, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 26 01 08 00 00 86 80 44 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0127, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 27 01 26 01 00 AE 0C 04 > > Handle 0x0128, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 28 01 08 00 00 86 80 45 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0129, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 29 01 28 01 00 AE 0C 05 > > Handle 0x012A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 2A 01 08 00 00 86 80 46 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x012B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 2B 01 2A 01 00 AE 0C 06 > > Handle 0x012C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 2C 01 08 00 00 86 80 47 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x012D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 2D 01 2C 01 00 AE 0C 07 > > Handle 0x012E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 2E 01 08 00 00 86 80 48 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x012F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 2F 01 2E 01 00 AE 0D 00 > > Handle 0x0130, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 30 01 08 00 00 86 80 49 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0131, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 31 01 30 01 00 AE 0D 01 > > Handle 0x0132, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 32 01 08 00 00 86 80 4A 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0133, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 33 01 32 01 00 AE 0D 02 > > Handle 0x0134, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 34 01 08 00 00 86 80 4B 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0135, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 35 01 34 01 00 AE 0D 03 > > Handle 0x0136, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 36 01 06 0E 00 86 80 30 20 D9 15 62 09 01 > 00 00 00 00 00 00 00 > > Handle 0x0137, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 37 01 36 01 00 D7 00 00 > > Handle 0x0138, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 38 01 06 0F 00 86 80 31 20 D9 15 62 09 01 > 00 00 00 00 00 00 00 > > Handle 0x0139, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 39 01 38 01 00 D7 01 00 > > Handle 0x013A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 3A 01 06 10 00 86 80 32 20 D9 15 62 09 01 > 00 00 00 00 00 00 00 > > Handle 0x013B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 3B 01 3A 01 00 D7 02 00 > > Handle 0x013C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 3C 01 06 11 00 86 80 33 20 D9 15 62 09 01 > 00 00 00 00 00 00 00 > > Handle 0x013D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 3D 01 3C 01 00 D7 03 00 > > Handle 0x013E, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 3E 01 08 00 00 86 80 34 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x013F, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 3F 01 3E 01 00 D7 05 00 > > Handle 0x0140, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 40 01 08 00 00 86 80 35 20 00 00 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0141, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 41 01 40 01 00 D7 05 02 > > Handle 0x0142, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 42 01 08 00 00 86 80 36 20 86 80 36 20 00 > 00 00 00 00 00 00 00 > > Handle 0x0143, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 43 01 42 01 00 D7 05 04 > > Handle 0x0144, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 44 01 11 00 00 86 80 58 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0145, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 45 01 44 01 00 D7 0E 00 > > Handle 0x0146, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 46 01 08 00 00 86 80 59 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0147, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 47 01 46 01 00 D7 0E 01 > > Handle 0x0148, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 48 01 11 00 00 86 80 58 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x0149, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 49 01 48 01 00 D7 0F 00 > > Handle 0x014A, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 4A 01 08 00 00 86 80 59 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x014B, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 4B 01 4A 01 00 D7 0F 01 > > Handle 0x014C, DMI type 192, 23 bytes > OEM-specific Type > Header and Data: > C0 17 4C 01 11 00 00 86 80 4C 20 86 80 00 00 00 > 00 00 00 00 00 00 00 > > Handle 0x014D, DMI type 165, 10 bytes > OEM-specific Type > Header and Data: > A5 0A 4D 01 4C 01 00 D7 12 00 > > Handle 0x014E, DMI type 193, 230 bytes > OEM-specific Type > Header and Data: > C1 E6 4E 01 01 01 16 00 00 00 47 65 6E 75 6E 74 > 65 6C 69 6E 65 49 54 06 05 00 00 08 10 00 FF FB > FE 77 FF FB EB BF 01 63 03 76 FF B5 F0 00 00 00 > 00 00 00 00 C3 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 40 00 00 00 40 00 00 00 03 00 > 00 00 20 20 00 00 77 00 00 00 02 00 00 00 09 00 > 00 00 00 00 00 00 00 00 00 00 FB FF 9F D3 08 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 04 04 30 07 00 00 00 00 00 00 > 00 00 03 06 00 00 01 00 00 00 02 00 00 00 00 01 > 00 00 00 00 00 00 FF 02 00 00 80 0A 00 00 88 0A > 00 00 00 00 00 00 00 00 00 00 3F 00 00 00 00 00 > 00 00 02 00 00 00 00 00 00 00 0A 00 00 00 00 00 > 00 00 00 00 00 00 > Strings: > Socket 0 > > Handle 0x014F, DMI type 193, 246 bytes > OEM-specific Type > Header and Data: > C1 F6 4F 01 01 02 01 00 00 00 0F 00 00 00 07 00 > 00 00 00 00 00 00 02 00 00 00 90 00 00 00 00 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 00 00 80 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 01 > 00 00 00 08 10 2C 49 6E 74 65 6C 28 52 29 20 58 > 65 6F 6E 28 52 29 20 53 69 6C 76 65 72 20 34 31 > 30 38 20 43 50 55 20 40 20 31 2E 38 30 47 48 7A > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 60 > 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 01 00 00 2E 30 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 > Strings: > Socket 0 > > Handle 0x0150, DMI type 193, 230 bytes > OEM-specific Type > Header and Data: > C1 E6 50 01 01 01 16 00 00 00 47 65 6E 75 6E 74 > 65 6C 69 6E 65 49 54 06 05 00 00 08 10 10 FF FB > FE 77 FF FB EB BF 01 63 03 76 FF B5 F0 00 00 00 > 00 00 00 00 C3 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 40 00 00 00 40 00 00 00 03 00 > 00 00 20 20 00 00 77 00 00 00 02 00 00 00 09 00 > 00 00 00 00 00 00 00 00 00 00 FB FF 9F D3 08 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 04 04 30 07 00 00 00 00 00 00 > 00 00 03 06 00 00 01 00 00 00 02 00 00 00 00 01 > 00 00 10 00 00 00 FF 02 00 00 80 0A 00 00 88 0A > 00 00 00 00 00 00 00 00 00 00 3F 00 00 00 00 00 > 00 00 02 00 00 00 00 00 00 00 0A 00 00 00 00 00 > 00 00 00 00 00 00 > Strings: > Socket 1 > > Handle 0x0151, DMI type 193, 246 bytes > OEM-specific Type > Header and Data: > C1 F6 51 01 01 02 01 00 00 00 0F 00 00 00 07 00 > 00 00 00 00 00 00 02 00 00 00 90 00 00 00 00 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 07 00 00 B8 0B 00 00 64 00 > 00 00 00 00 00 00 08 00 00 80 00 00 00 00 00 00 > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 01 > 00 00 00 08 10 2C 49 6E 74 65 6C 28 52 29 20 58 > 65 6F 6E 28 52 29 20 53 69 6C 76 65 72 20 34 31 > 30 38 20 43 50 55 20 40 20 31 2E 38 30 47 48 7A > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 60 > 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 > 00 00 00 01 00 00 2E 30 00 00 00 00 00 00 00 00 > 00 00 00 00 00 00 > Strings: > Socket 1 > > Handle 0x0152, DMI type 196, 5 bytes > OEM-specific Type > Header and Data: > C4 05 52 01 00 > > Handle 0x0153, DMI type 127, 4 bytes > End Of Table > > > -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer

3 14

[PATCH 00/40] [Set 14] Rid W=1 warnings from GPU
by Lee Jones 18 Jan '21

18 Jan '21

This set is part of a larger effort attempting to clean-up W=1 kernel builds, which are currently overwhelmingly riddled with niggly little warnings. Penultimate set, promise. :) Lee Jones (40): drm/r128/r128_ioc32: Document headers do not make good kernel-doc candidates drm/mga/mga_ioc32: Document headers do not make good kernel-doc candidates drm/vmwgfx/vmwgfx_execbuf: Fix some kernel-doc related issues drm/vmwgfx/vmwgfx_kms: Remove unused variable 'ret' from 'vmw_du_primary_plane_atomic_check()' drm/r128/r128_ioc32: Fix formatting issues in 'r128_compat_ioctl()'s header drm/mga/mga_ioc32: Fix some formatting issues in 'mga_compat_ioctl's header drm/vmwgfx/vmwgfx_kms: Mark vmw_{cursor,primary}_plane_formats as __maybe_unused drm/vmwgfx/vmwgfx_drv: Fix some kernel-doc misdemeanours drm/vmwgfx/vmwgfx_ioctl: Provide missing '@' sign required by kernel-doc drm/vmwgfx/vmwgfx_resource: Fix worthy function headers demote some others drm/vmwgfx/vmwgfx_ttm_buffer: Supply some missing parameter descriptions drm/vmwgfx/vmwgfx_fifo: Demote non-conformant kernel-doc header drm/vmwgfx/vmwgfx_ldu: Supply descriptions for 'state' function parameter drm/gma500/framebuffer: Fix some possible doc-rot issues drm/gma500/gem: Add and rename some function parameter descriptions drm/gma500/intel_bios: Demote non-conformant kernel-doc header drm/gma500/intel_i2c: Remove superflouous parameter description and rename another drm/gma500/mmu: Make local function 'psb_mmu_pt_alloc_map_lock()' static drm/gma500/power: Fix a bunch of *dev documentation issues drm/vmwgfx/vmwgfx_kms: Update worthy function headers and demote others drm/gma500/gma_display: Demote kernel-doc abuses to standard comment blocks drm/gma500/gma_device: Include our own header containing prototypes drm/vmwgfx/vmwgfx_overlay: Demote kernel-doc abuses to standard comment blocks drm/gma500/psb_intel_display: Demote kernel-doc formatting abuse drm/gma500/psb_intel_lvds: Supply description for 'mode_dev' drm/vmwgfx/vmwgfx_fence: Add, remove and demote various documentation params/headers drm/vmwgfx/vmwgfx_bo: Remove superfluous param description and supply another drm/vmwgfx/vmwgfx_context: Demote kernel-doc abuses drm/vmwgfx/vmwgfx_scrn: Demote unworthy kernel-doc headers and update others drm/gma500/psb_intel_modes: Provide missing descriptions for function param 'adapter' drm/gma500/gem: Do not rely on consumers to include drm/drm_device.h before gem.h drm/gma500/gem: Include our own header containing prototypes drm/vmwgfx/vmwgfx_surface: Fix some kernel-doc related issues drm/gma500/mmu: Remove unused function 'psb_get_default_pd_addr' drm/vmwgfx/vmwgfx_cmdbuf_res: Rename param description and remove another drm/vmwgfx/vmwgfx_shader: Demote kernel-doc abuses and fix-up worthy headers drm/vmwgfx/vmwgfx_cmdbuf: Fix a bunch of missing or incorrectly formatted/named params drm/gma500/power: Remove excess param description 'state' drm/vmwgfx/vmwgfx_cmdbuf_res: Remove unused variable 'ret' drm/vmwgfx/vmwgfx_stdu: Add some missing param/member descriptions drivers/gpu/drm/gma500/framebuffer.c | 6 +++--- drivers/gpu/drm/gma500/gem.c | 6 ++++-- drivers/gpu/drm/gma500/gem.h | 2 ++ drivers/gpu/drm/gma500/gma_device.c | 1 + drivers/gpu/drm/gma500/gma_display.c | 8 ++++---- drivers/gpu/drm/gma500/intel_bios.c | 2 +- drivers/gpu/drm/gma500/intel_i2c.c | 3 +-- drivers/gpu/drm/gma500/mmu.c | 13 ++----------- drivers/gpu/drm/gma500/power.c | 8 ++++---- drivers/gpu/drm/gma500/psb_intel_display.c | 2 +- drivers/gpu/drm/gma500/psb_intel_lvds.c | 1 + drivers/gpu/drm/gma500/psb_intel_modes.c | 3 ++- drivers/gpu/drm/mga/mga_ioc32.c | 14 +++++++------- drivers/gpu/drm/r128/r128_ioc32.c | 14 +++++++------- drivers/gpu/drm/vmwgfx/vmwgfx_bo.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c | 12 ++++++++---- drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c | 8 ++------ drivers/gpu/drm/vmwgfx/vmwgfx_context.c | 6 +++--- drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 8 ++++---- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 20 ++++++++++++-------- drivers/gpu/drm/vmwgfx/vmwgfx_fence.c | 18 ++++++++++-------- drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c | 2 +- drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 16 ++++++++-------- drivers/gpu/drm/vmwgfx/vmwgfx_kms.h | 4 ++-- drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c | 4 +++- drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c | 16 ++++++++-------- drivers/gpu/drm/vmwgfx/vmwgfx_resource.c | 10 ++++------ drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 10 ++++++---- drivers/gpu/drm/vmwgfx/vmwgfx_shader.c | 10 +++++----- drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 9 +++++++-- drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 17 ++++++++++------- drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 2 ++ 33 files changed, 137 insertions(+), 122 deletions(-) Cc: Alan Cox <alan(a)linux.intel.com> Cc: Benjamin Defnet <benjamin.r.defnet(a)intel.com> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: David Airlie <airlied(a)linux.ie> Cc: dri-devel(a)lists.freedesktop.org Cc: Eric Anholt <eric(a)anholt.net> Cc: Jesse Barnes <jesse.barnes(a)intel.com> Cc: Lee Jones <lee.jones(a)linaro.org> Cc: linaro-mm-sig(a)lists.linaro.org Cc: linux-media(a)vger.kernel.org Cc: Patrik Jakobsson <patrik.r.jakobsson(a)gmail.com> Cc: Rajesh Poornachandran <rajesh.poornachandran(a)intel.com> Cc: Roland Scheidegger <sroland(a)vmware.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: VMware Graphics <linux-graphics-maintainer(a)vmware.com> Cc: Zack Rusin <zackr(a)vmware.com> -- 2.25.1

3 42

[PATCH] drm/vram-helper: Reuse existing page mappings in vmap
by Thomas Zimmermann 18 Jan '21

18 Jan '21

For performance, BO page mappings can stay in place even if the map counter has returned to 0. In these cases, the existing page mapping has to be reused by the next vmap operation. Otherwise a new mapping would be installed and the old mapping's pages leak. Fix the issue by reusing existing page mappings for vmap operations. Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Fixes: 1086db71a1db ("drm/vram-helper: Remove invariant parameters from internal kmap function") Acked-by: Christian König <christian.koenig(a)amd.com> Tested-by: Eli Cohen <elic(a)nvidia.com> Reported-by: Eli Cohen <elic(a)nvidia.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: Christian König <christian.koenig(a)amd.com> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Maxime Ripard <mripard(a)kernel.org> Cc: David Airlie <airlied(a)linux.ie> Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: dri-devel(a)lists.freedesktop.org --- drivers/gpu/drm/drm_gem_vram_helper.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index 02ca22e90290..0b232a73c1b7 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -387,9 +387,16 @@ static int drm_gem_vram_kmap_locked(struct drm_gem_vram_object *gbo, if (gbo->vmap_use_count > 0) goto out; - ret = ttm_bo_vmap(&gbo->bo, &gbo->map); - if (ret) - return ret; + /* + * VRAM helpers unmap the BO only on demand. So the previous + * page mapping might still be around. Only vmap if the there's + * no mapping present. + */ + if (dma_buf_map_is_null(&gbo->map)) { + ret = ttm_bo_vmap(&gbo->bo, &gbo->map); + if (ret) + return ret; + } out: ++gbo->vmap_use_count; @@ -577,6 +584,7 @@ static void drm_gem_vram_bo_driver_move_notify(struct drm_gem_vram_object *gbo, return; ttm_bo_vunmap(bo, &gbo->map); + dma_buf_map_clear(&gbo->map); /* explicitly clear mapping for next vmap call */ } static int drm_gem_vram_bo_driver_move(struct drm_gem_vram_object *gbo, -- 2.29.2

1 0

← Newer
1
...
43
44
45
46
47
48
49
...
74
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

dri-devel January 2021