dri-devel December 2021

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720 discussions

[PATCH] drm/i915/guc: Request RP0 before loading firmware
by Vinay Belgaumkar 09 Dec '21

09 Dec '21

By default, GT (and GuC) run at RPn. Requesting for RP0 before firmware load can speed up DMA and HuC auth as well. In addition to writing to 0xA008, we also need to enable swreq in 0xA024 so that Punit will pay heed to our request. SLPC will restore the frequency back to RPn after initialization, but we need to manually do that for the non-SLPC path. Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar(a)intel.com> --- drivers/gpu/drm/i915/gt/intel_rps.c | 59 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_rps.h | 2 + drivers/gpu/drm/i915/gt/uc/intel_uc.c | 9 ++++ drivers/gpu/drm/i915/i915_reg.h | 4 ++ 4 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 07ff7ba7b2b7..4f7fe079ed4a 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -2226,6 +2226,65 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps) return intel_uncore_read(uncore, GEN6_RP_STATE_CAP); } +static void intel_rps_set_manual(struct intel_rps *rps, bool enable) +{ + struct intel_uncore *uncore = rps_to_uncore(rps); + u32 state = enable ? GEN9_RPSWCTL_ENABLE : GEN9_RPSWCTL_DISABLE; + + if (enable) + intel_rps_clear_timer(rps); + + /* Allow punit to process software requests */ + intel_uncore_write(uncore, GEN6_RP_CONTROL, state); + + if (!enable) + intel_rps_set_timer(rps); +} + +void intel_rps_raise_unslice(struct intel_rps *rps) +{ + struct intel_uncore *uncore = rps_to_uncore(rps); + u32 rp0_unslice_req; + + intel_rps_set_manual(rps, true); + + /* RP limits have not been read yet */ + if (!rps->rp0_freq) + rp0_unslice_req = ((intel_rps_read_state_cap(rps) >> 0) + & 0xff) * GEN9_FREQ_SCALER; + else + rp0_unslice_req = rps->rp0_freq; + + intel_uncore_write(uncore, GEN6_RPNSWREQ, + ((rp0_unslice_req << + GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | + GEN9_IGNORE_SLICE_RATIO)); + + intel_rps_set_manual(rps, false); +} + +void intel_rps_lower_unslice(struct intel_rps *rps) +{ + struct intel_uncore *uncore = rps_to_uncore(rps); + u32 rpn_unslice_req; + + intel_rps_set_manual(rps, true); + + /* RP limits have not been read yet */ + if (!rps->min_freq) + rpn_unslice_req = ((intel_rps_read_state_cap(rps) >> 16) + & 0xff) * GEN9_FREQ_SCALER; + else + rpn_unslice_req = rps->min_freq; + + intel_uncore_write(uncore, GEN6_RPNSWREQ, + ((rpn_unslice_req << + GEN9_SW_REQ_UNSLICE_RATIO_SHIFT) | + GEN9_IGNORE_SLICE_RATIO)); + + intel_rps_set_manual(rps, false); +} + /* External interface for intel_ips.ko */ static struct drm_i915_private __rcu *ips_mchdev; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h index aee12f37d38a..c6d76a3d1331 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.h +++ b/drivers/gpu/drm/i915/gt/intel_rps.h @@ -45,6 +45,8 @@ u32 intel_rps_get_rpn_frequency(struct intel_rps *rps); u32 intel_rps_read_punit_req(struct intel_rps *rps); u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps); u32 intel_rps_read_state_cap(struct intel_rps *rps); +void intel_rps_raise_unslice(struct intel_rps *rps); +void intel_rps_lower_unslice(struct intel_rps *rps); void gen5_rps_irq_handler(struct intel_rps *rps); void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 2fef3b0bbe95..3693c4e7dad0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -8,6 +8,7 @@ #include "intel_guc.h" #include "intel_guc_ads.h" #include "intel_guc_submission.h" +#include "gt/intel_rps.h" #include "intel_uc.h" #include "i915_drv.h" @@ -462,6 +463,8 @@ static int __uc_init_hw(struct intel_uc *uc) else attempts = 1; + intel_rps_raise_unslice(&uc_to_gt(uc)->rps); + while (attempts--) { /* * Always reset the GuC just before (re)loading, so @@ -499,6 +502,9 @@ static int __uc_init_hw(struct intel_uc *uc) ret = intel_guc_slpc_enable(&guc->slpc); if (ret) goto err_submission; + } else { + /* Restore GT back to RPn for non-SLPC path */ + intel_rps_lower_unslice(&uc_to_gt(uc)->rps); } drm_info(&i915->drm, "%s firmware %s version %u.%u %s:%s\n", @@ -529,6 +535,9 @@ static int __uc_init_hw(struct intel_uc *uc) err_log_capture: __uc_capture_load_err_log(uc); err_out: + /* Return GT back to RPn */ + intel_rps_lower_unslice(&uc_to_gt(uc)->rps); + __uc_sanitize(uc); if (!ret) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1891e7fac39b..b2a86a26b843 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9399,6 +9399,7 @@ enum { #define GEN6_OFFSET(x) ((x) << 19) #define GEN6_AGGRESSIVE_TURBO (0 << 15) #define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23 +#define GEN9_IGNORE_SLICE_RATIO (0 << 0) #define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C) #define GEN6_RC_CONTROL _MMIO(0xA090) @@ -9434,6 +9435,9 @@ enum { #define GEN6_RP_UP_BUSY_CONT (0x4 << 3) #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) +#define GEN6_RPSWCTL_SHIFT 9 +#define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT) +#define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT) #define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C) #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030) #define GEN6_RP_CUR_UP_EI _MMIO(0xA050) -- 2.34.0

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[PATCH] drm: Remove some useless memset
by Christophe JAILLET 09 Dec '21

09 Dec '21

'bufs' is an array embedded in an structure (struct drm_device_dma) which is kzalloc just a few lines above. So there is no need to explicitly memset each element on the array. It is already cleared. Remove the useless memset. Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- drivers/gpu/drm/drm_dma.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/drm_dma.c b/drivers/gpu/drm/drm_dma.c index eb6b741a6f99..df4837dc5030 100644 --- a/drivers/gpu/drm/drm_dma.c +++ b/drivers/gpu/drm/drm_dma.c @@ -51,8 +51,6 @@ */ int drm_legacy_dma_setup(struct drm_device *dev) { - int i; - if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA) || !drm_core_check_feature(dev, DRIVER_LEGACY)) return 0; @@ -64,9 +62,6 @@ int drm_legacy_dma_setup(struct drm_device *dev) if (!dev->dma) return -ENOMEM; - for (i = 0; i <= DRM_MAX_ORDER; i++) - memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0])); - return 0; } -- 2.32.0

1 0

[PATCH v4 RESEND 0/2] GPD Win Max display fixes
by Anisse Astier 09 Dec '21

09 Dec '21

This patch series is for making the GPD Win Max display usable with Linux. The GPD Win Max is a small laptop, and its eDP panel does not send an EDID over DPCD; the EDID is instead available in the intel opregion, in mailbox #5 [1] The second patch is just to fix the orientation of the panel. Changes since v1: - rebased on drm-tip - squashed patch 1 & 2 - picked up Reviewed-by from Hans de Goede (thanks for the review) Changes since v2: - rebased on drm-tip - updated commit message When v2 was initially sent [3] Ville Syrjälä suggested that it might be a good idea to use the ACPI _DDC method instead to get the EDID, to cover a wider range of hardware. Unfortunately, it doesn't seem available on GPD Win Max, so I think this work should be done independently, and this patch series considered separately. Change since v3: - edits following Jani's review: - The EDID from the opregion is now only used as a fallback: if we cannot get any edid from the edp connector, then we attempt to get it from the opregion. This works for the GPD Win Max. - all other remarks should have been taken into account - rebased on drm-tip - added Co-developed-by - reordered signed-off-by and reviewed-by in second patch (thanks Maarten!) [1]: https://gitlab.freedesktop.org/drm/intel/-/issues/3454 [2]: https://patchwork.kernel.org/project/intel-gfx/patch/20200828061941.17051-1… [3]: https://patchwork.kernel.org/project/intel-gfx/patch/20210531204642.4907-2-… Anisse Astier (2): drm/i915/opregion: add support for mailbox #5 EDID drm: Add orientation quirk for GPD Win Max .../gpu/drm/drm_panel_orientation_quirks.c | 6 ++ drivers/gpu/drm/i915/display/intel_dp.c | 7 +++ drivers/gpu/drm/i915/display/intel_opregion.c | 55 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_opregion.h | 10 ++++ 4 files changed, 77 insertions(+), 1 deletion(-) -- 2.31.1

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[PATCH v7 1/2] drm/msm/dp: dp_link_parse_sink_count() return immediately if aux read failed
by Kuogee Hsieh 09 Dec '21

09 Dec '21

Add checking aux read/write status at both dp_link_parse_sink_count() and dp_link_parse_sink_status_filed() to avoid long timeout delay if dp aux read/write failed at timeout due to cable unplugged. Also make sure dp controller had been initialized before start dpcd read and write. Changes in V4: -- split this patch as stand alone patch Changes in v5: -- rebase on msm-next branch Changes in v6: -- add more details commit text Signed-off-by: Kuogee Hsieh <quic_khsieh(a)quicinc.com> Reviewed-by: Stephen Boyd <swboyd(a)chromium.org> Tested-by: Stephen Boyd <swboyd(a)chromium.org> --- drivers/gpu/drm/msm/dp/dp_display.c | 12 +++++++++--- drivers/gpu/drm/msm/dp/dp_link.c | 19 ++++++++++++++----- 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 3d61459..0766752 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -692,9 +692,15 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) return 0; } - ret = dp_display_usbpd_attention_cb(&dp->pdev->dev); - if (ret == -ECONNRESET) { /* cable unplugged */ - dp->core_initialized = false; + /* + * dp core (ahb/aux clks) must be initialized before + * irq_hpd be handled + */ + if (dp->core_initialized) { + ret = dp_display_usbpd_attention_cb(&dp->pdev->dev); + if (ret == -ECONNRESET) { /* cable unplugged */ + dp->core_initialized = false; + } } DRM_DEBUG_DP("hpd_state=%d\n", state); diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c index a5bdfc5..d4d31e5 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -737,18 +737,25 @@ static int dp_link_parse_sink_count(struct dp_link *dp_link) return 0; } -static void dp_link_parse_sink_status_field(struct dp_link_private *link) +static int dp_link_parse_sink_status_field(struct dp_link_private *link) { int len = 0; link->prev_sink_count = link->dp_link.sink_count; - dp_link_parse_sink_count(&link->dp_link); + len = dp_link_parse_sink_count(&link->dp_link); + if (len < 0) { + DRM_ERROR("DP parse sink count failed\n"); + return len; + } len = drm_dp_dpcd_read_link_status(link->aux, link->link_status); - if (len < DP_LINK_STATUS_SIZE) + if (len < DP_LINK_STATUS_SIZE) { DRM_ERROR("DP link status read failed\n"); - dp_link_parse_request(link); + return len; + } + + return dp_link_parse_request(link); } /** @@ -1023,7 +1030,9 @@ int dp_link_process_request(struct dp_link *dp_link) dp_link_reset_data(link); - dp_link_parse_sink_status_field(link); + ret = dp_link_parse_sink_status_field(link); + if (ret) + return ret; if (link->request.test_requested == DP_TEST_LINK_EDID_READ) { dp_link->sink_request |= DP_TEST_LINK_EDID_READ; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

1 0

[PATCH] drm/i915/guc: Remove racey GEM_BUG_ON
by Matthew Brost 09 Dec '21

09 Dec '21

A full GT can race with the last context put resulting in the context ref count being zero but the destroyed bit not yet being set. Remove GEM_BUG_ON in scrub_guc_desc_for_outstanding_g2h that asserts the destroyed bit must be set in ref count is zero. Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 9b7b4f4e0d91..0f99bb83293a 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1040,8 +1040,6 @@ static void scrub_guc_desc_for_outstanding_g2h(struct intel_guc *guc) spin_unlock(&ce->guc_state.lock); - GEM_BUG_ON(!do_put && !destroyed); - if (pending_enable || destroyed || deregister) { decr_outstanding_submission_g2h(guc); if (deregister) -- 2.33.1

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[PATCH] drm/msm/a6xx: Skip crashdumper state if GPU needs_hw_init
by Rob Clark 09 Dec '21

09 Dec '21

From: Rob Clark <robdclark(a)chromium.org> I am seeing some crash logs which imply that we are trying to use crashdumper hw to read back GPU state when the GPU isn't initialized. This doesn't go well (for example, GPU could be in 32b address mode and ignoring the upper bits of buffer that it is trying to dump state to). I'm not *quite* sure how we get into this state in the first place, but lets not make a bad situation worse by triggering iova fault crashes. While we're at it, also add the information about whether the GPU is initialized to the devcore dump to make this easier to see in the logs (which makes the WARN_ON() redundant and even harmful because it fills up the small bit of dmesg we get with the crash report). Signed-off-by: Rob Clark <robdclark(a)chromium.org> --- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 9 ++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index bdd0059a81ff..55f443328d8e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -49,6 +49,8 @@ struct a6xx_gpu_state { s32 hfi_queue_history[2][HFI_HISTORY_SZ]; struct list_head objs; + + bool gpu_initialized; }; static inline int CRASHDUMP_WRITE(u64 *in, u32 reg, u32 val) @@ -1001,7 +1003,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) * write out GPU state, so we need to skip this when the SMMU is * stalled in response to an iova fault */ - if (!stalled && !a6xx_crashdumper_init(gpu, &_dumper)) { + if (!stalled && !gpu->needs_hw_init && + !a6xx_crashdumper_init(gpu, &_dumper)) { dumper = &_dumper; } @@ -1018,6 +1021,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) if (snapshot_debugbus) a6xx_get_debugbus(gpu, a6xx_state); + a6xx_state->gpu_initialized = !gpu->needs_hw_init; + return &a6xx_state->base; } @@ -1246,6 +1251,8 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, if (IS_ERR_OR_NULL(state)) return; + drm_printf(p, "gpu-initialized: %d\n", a6xx_state->gpu_initialized); + adreno_show(gpu, state, p); drm_puts(p, "gmu-log:\n"); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 47cb40bdbd43..f33cfa4ef1c8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -504,7 +504,6 @@ int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i, count = 0; - WARN_ON(gpu->needs_hw_init); WARN_ON(!mutex_is_locked(&gpu->lock)); kref_init(&state->ref); -- 2.33.1

1 0

[PULL] drm-intel-fixes
by Rodrigo Vivi 09 Dec '21

09 Dec '21

Hi Dave and Daniel, Here goes drm-intel-fixes-2021-12-09: A fix to a error pointer dereference in gem_execbuffer and a fix for GT initialization when GuC/HuC are used on ICL. Thanks, Rodrigo. The following changes since commit 0fcfb00b28c0b7884635dacf38e46d60bf3d4eb1: Linux 5.16-rc4 (2021-12-05 14:08:22 -0800) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-fixes-2021-12-09 for you to fetch changes up to 52255ef662a5d490678fbad64a735f88fcba564d: drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() (2021-12-09 08:30:22 -0500) ---------------------------------------------------------------- A fix to a error pointer dereference in gem_execbuffer and a fix for GT initialization when GuC/HuC are used on ICL. ---------------------------------------------------------------- Dan Carpenter (1): drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer() Raviteja Goud Talla (1): drm/i915/gen11: Moving WAs to icl_gt_workarounds_init() drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++--------- 2 files changed, 10 insertions(+), 9 deletions(-)

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[PATCH] drm/i915: Fix coredump of perma-pinned vmas
by Thomas Hellström 09 Dec '21

09 Dec '21

When updating the error capture code and introducing vma snapshots, we introduced code to hold the vma in memory while capturing it, calling i915_active_acquire_if_busy(). Now that function isn't relevant for perma-pinned vmas and caused important vmas to be dropped from the coredump. Like for example the GuC log. Fix this by instead requiring those vmas to be pinned while capturing. Tested by running the initial subtests of the gem_exec_capture igt test with GuC submission enabled and verifying that a GuC log blob appears in the output. Fixes: ff20afc4cee7 ("drm/i915: Update error capture code to avoid using the current vma state") Cc: Ramalingam C <ramalingam.c(a)intel.com> Cc: Matthew Auld <matthew.auld(a)intel.com> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: John Harrison <John.C.Harrison(a)Intel.com> Cc: Matthew Brost <matthew.brost(a)intel.com> Reported-by: John Harrison <John.C.Harrison(a)Intel.com> Signed-off-by: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> --- drivers/gpu/drm/i915/i915_gpu_error.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 96d2d99f5b98..e06d3aee0017 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1415,18 +1415,15 @@ static struct i915_vma_coredump * create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma, const char *name, struct i915_vma_compress *compress) { - struct i915_vma_coredump *ret = NULL; + struct i915_vma_coredump *ret; struct i915_vma_snapshot tmp; - bool lockdep_cookie; if (!vma) return NULL; + GEM_WARN_ON(!i915_vma_is_pinned(vma)); i915_vma_snapshot_init_onstack(&tmp, vma, name); - if (i915_vma_snapshot_resource_pin(&tmp, &lockdep_cookie)) { - ret = i915_vma_coredump_create(gt, &tmp, compress); - i915_vma_snapshot_resource_unpin(&tmp, lockdep_cookie); - } + ret = i915_vma_coredump_create(gt, &tmp, compress); i915_vma_snapshot_put_onstack(&tmp); return ret; -- 2.31.1

2 1

[PATCH 0/2] drm: of: Lookup child panel_or_bridge
by Jagan Teki 09 Dec '21

09 Dec '21

This patch set add support to lookup if child node is panel or bridge via drm_of_find_panel_or_bridge. Any inputs? Jagan. Jagan Teki (2): of: Add helper to lookup non port child node drm: of: Lookup if child node is panel or bridge drivers/gpu/drm/drm_of.c | 36 ++++++++++++++++++++++++++---------- drivers/of/base.c | 29 +++++++++++++++++++++++++++++ include/linux/of.h | 6 ++++++ 3 files changed, 61 insertions(+), 10 deletions(-) -- 2.25.1

2 5

[PATCH] drm/i915: Don't leak the capture list items
by Thomas Hellström 09 Dec '21

09 Dec '21

When we recently converted the capture code to use vma snapshots, we forgot to free the struct i915_capture_list list items after use. Fix that by bringing back a kfree. Fixes: ff20afc4cee7 ("drm/i915: Update error capture code to avoid using the current vma state") Cc: Ramalingam C <ramalingam.c(a)intel.com> Signed-off-by: Thomas Hellström <thomas.hellstrom(a)linux.intel.com> --- drivers/gpu/drm/i915/i915_request.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 471cde0e9883..fe682b6902aa 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -307,6 +307,7 @@ void i915_request_free_capture_list(struct i915_capture_list *capture) struct i915_capture_list *next = capture->next; i915_vma_snapshot_put(capture->vma_snapshot); + kfree(capture); capture = next; } } -- 2.31.1

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dri-devel December 2021