dri-devel April 2021

dri-devel@lists.freedesktop.org

317 participants
715 discussions

[PATCH] drm/amdgpu: Fix a potential sdma invalid access
by Qu Huang 06 Apr '21

06 Apr '21

Before dma_resv_lock(bo->base.resv, NULL) in amdgpu_bo_release_notify(), the bo->base.resv lock may be held by ttm_mem_evict_first(), and the VRAM mem will be evicted, mem region was replaced by Gtt mem region. amdgpu_bo_release_notify() will then hold the bo->base.resv lock, and SDMA will get an invalid address in amdgpu_fill_buffer(), resulting in a VMFAULT or memory corruption. To avoid it, we have to hold bo->base.resv lock first, and check whether the mem.mem_type is TTM_PL_VRAM. Signed-off-by: Qu Huang <jinsdb(a)126.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 4b29b82..8018574 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1300,12 +1300,16 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) if (bo->base.resv == &bo->base._resv) amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); - if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || - !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) + if (!(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) return; dma_resv_lock(bo->base.resv, NULL); + if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node) { + dma_resv_unlock(bo->base.resv); + return; + } + r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); if (!WARN_ON(r)) { amdgpu_bo_fence(abo, fence, false); -- 1.8.3.1

3 6

[PULL] drm-intel-gt-next
by Joonas Lahtinen 06 Apr '21

06 Apr '21

Hi Dave & Daniel, Bit late PR due to Easter break. Prep work for local memory support as requested. Hard hang fix for Sandybridge. Sanitize dma-buf size on import and avoid GPU reset if heartbeat callback runs before timeout. The rest is mostly small fixes and code/checkpatch cleanups. Regards, Joonas *** drm-intel-gt-next-2021-04-06: Driver Changes: - Prepare for local/device memory support on DG1 by starting to use it for kernel internal allocations: context, ring and engine scratch (Matt A, CQ, Abdiel, Imre) - Sandybridge fix to avoid hard hang on ring resume (Chris) - Limit imported dma-buf size to int32 (Matt A) - Double check heartbeat timeout before resetting (Chris) - Use new tasklet API for execution list (Emil) - Fix SPDX checkpats warnings (Chris) - Fixes for various checkpatch warnings (Chris) - Selftest improvements (Chris) - Move the defer_request waiter active assertion to correct spot (Chris) - Make local-memory probing a GT operation (Matt, Tvrtko) - Protect against request freeing during cancellation on wedging (Chris) - Retire unexpected starting state error dumping (Chris) - Distinction of memory regions in debugging (Zbigniew) - Always flush the submission queue on checking for idle (Chris) - Consolidate 2big error check to helper (Matt) - Decrease number of subplatform bits (Tvrtko) - Remove unused internal request priority levels (Chris) - Document the unused internal header bits in buddy allocator (Matt) - Cleanup the region class/instance encoding (Matt) The following changes since commit 06debd6e1b28029e6e77c41e59a162868f377897: Merge tag 'drm-intel-next-2021-03-16' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (2021-03-18 08:06:34 +1000) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-gt-next-2021-04-06 for you to fetch changes up to 2da21daa7d93817fa82f703c29adfcb5eed7f77d: drm/i915/gt: Always flush the submission queue on checking for idle (2021-03-24 19:31:59 +0100) ---------------------------------------------------------------- Driver Changes: - Prepare for local/device memory support on DG1 by starting to use it for kernel internal allocations: context, ring and engine scratch (Matt A, CQ, Abdiel, Imre) - Sandybridge fix to avoid hard hang on ring resume (Chris) - Limit imported dma-buf size to int32 (Matt A) - Double check heartbeat timeout before resetting (Chris) - Use new tasklet API for execution list (Emil) - Fix SPDX checkpats warnings (Chris) - Fixes for various checkpatch warnings (Chris) - Selftest improvements (Chris) - Move the defer_request waiter active assertion to correct spot (Chris) - Make local-memory probing a GT operation (Matt, Tvrtko) - Protect against request freeing during cancellation on wedging (Chris) - Retire unexpected starting state error dumping (Chris) - Distinction of memory regions in debugging (Zbigniew) - Always flush the submission queue on checking for idle (Chris) - Consolidate 2big error check to helper (Matt) - Decrease number of subplatform bits (Tvrtko) - Remove unused internal request priority levels (Chris) - Document the unused internal header bits in buddy allocator (Matt) - Cleanup the region class/instance encoding (Matt) ---------------------------------------------------------------- Abdiel Janulgue (1): drm/i915: introduce mem->reserved CQ Tang (1): drm/i915: reserve stolen for LMEM region Chris Wilson (22): drm/i915: Strip out internal priorities drm/i915: Remove I915_USER_PRIORITY_SHIFT drm/i915/gt: Call stop_ring() from ring resume, again drm/i915/gt: SPDX cleanup drm/i915/gt: Add some missing blank lines after declaration drm/i915/gt: Remove repeated words from comments drm/i915/gt: Fixup misaligned function parameters drm/i915/gt: Remove a bonus newline drm/i915/gt: Wrap macro arg in () drm/i915/gt: Insert spaces into GEN3_L3LOG_SIZE/4 drm/i915/gt: Replace unnecessary ',' with '; ' drm/i915/gt: Add a space before '(' drm/i915/gt: Replace 'return' with a fall-through drm/i915/selftests: Check for engine-reset errors in the middle of workarounds drm/i915/gt: Move the defer_request waiter active assertion drm/i915: Protect against request freeing during cancellation on wedging drm/i915/selftests: Use a single copy of the mocs table drm/i915/gt: Retire unexpected starting state error dumping drm/i915/selftests: Restore previous heartbeat interval drm/i915/gt: Double check heartbeat timeout before resetting drm/i915/selftest: Synchronise with the GPU timestamp drm/i915/gt: Always flush the submission queue on checking for idle Emil Renner Berthing (1): drm/i915/gt: use new tasklet API for execution list Imre Deak (1): drm/i915/dg1: Reserve first 1MB of local memory Matthew Auld (11): drm/i915/gem: don't trust the dma_buf->size drm/i915/gem: consolidate 2big error checking for object sizes drm/i915/buddy: document the unused header bits drm/i915: make local-memory probing a GT operation drm/i915: setup the LMEM region drm/i915: allocate context from LMEM drm/i915: move engine scratch to LMEM drm/i915/gtt/dg1: add PTE_LM plumbing for ppGTT drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT drm/i915: cleanup the region class/instance encoding drm/i915: give stolen system memory its own class Michel Thierry (1): drm/i915: allocate cmd ring in lmem Tvrtko Ursulin (1): drm/i915: Decrease number of subplatform bits Zbigniew Kempczyński (1): drm/i915: Distinction of memory regions drivers/gpu/drm/i915/display/intel_display.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 3 + drivers/gpu/drm/i915/gem/i915_gem_object.h | 26 ++++ drivers/gpu/drm/i915/gem/i915_gem_region.c | 12 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 16 +-- .../drm/i915/gem/selftests/i915_gem_object_blt.c | 4 +- drivers/gpu/drm/i915/gt/debugfs_gt.c | 2 +- drivers/gpu/drm/i915/gt/gen6_ppgtt.h | 4 +- drivers/gpu/drm/i915/gt/gen6_renderstate.c | 20 +-- drivers/gpu/drm/i915/gt/gen7_renderstate.c | 20 +-- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 13 +- drivers/gpu/drm/i915/gt/gen8_renderstate.c | 20 +-- drivers/gpu/drm/i915/gt/gen9_renderstate.c | 20 +-- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 23 +--- drivers/gpu/drm/i915/gt/intel_context.c | 3 +- drivers/gpu/drm/i915/gt/intel_context.h | 3 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 35 +---- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c | 26 ++-- drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_pm.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_engine_user.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_user.h | 3 +- .../gpu/drm/i915/gt/intel_execlists_submission.c | 97 +++++--------- drivers/gpu/drm/i915/gt/intel_ggtt.c | 26 +++- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 23 +--- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h | 21 +-- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 3 +- drivers/gpu/drm/i915/gt/intel_gt.c | 44 ++++++- drivers/gpu/drm/i915/gt/intel_gt.h | 1 + .../gpu/drm/i915/gt/intel_gt_buffer_pool_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 1 - drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 3 +- drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h | 3 +- drivers/gpu/drm/i915/gt/intel_gt_requests.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt_requests.h | 3 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 5 + drivers/gpu/drm/i915/gt/intel_llc.c | 3 +- drivers/gpu/drm/i915/gt/intel_llc.h | 3 +- drivers/gpu/drm/i915/gt/intel_llc_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 5 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 21 +-- drivers/gpu/drm/i915/gt/intel_mocs.h | 22 +--- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 4 + drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +- drivers/gpu/drm/i915/gt/intel_rc6.h | 3 +- drivers/gpu/drm/i915/gt/intel_rc6_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 97 +++++++++++++- drivers/gpu/drm/i915/gt/intel_region_lmem.h | 6 +- drivers/gpu/drm/i915/gt/intel_renderstate.c | 27 +--- drivers/gpu/drm/i915/gt/intel_renderstate.h | 20 +-- drivers/gpu/drm/i915/gt/intel_reset.c | 18 +-- drivers/gpu/drm/i915/gt/intel_reset.h | 3 +- drivers/gpu/drm/i915/gt/intel_reset_types.h | 2 +- drivers/gpu/drm/i915/gt/intel_ring.c | 8 +- drivers/gpu/drm/i915/gt/intel_ring.h | 4 +- drivers/gpu/drm/i915/gt/intel_ring_submission.c | 146 +++++++++------------ drivers/gpu/drm/i915/gt/intel_ring_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_rps.c | 3 +- drivers/gpu/drm/i915/gt/intel_rps.h | 3 +- drivers/gpu/drm/i915/gt/intel_rps_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 3 +- drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +- drivers/gpu/drm/i915/gt/intel_timeline.c | 3 +- drivers/gpu/drm/i915/gt/intel_timeline.h | 21 +-- drivers/gpu/drm/i915/gt/intel_timeline_types.h | 3 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +- drivers/gpu/drm/i915/gt/intel_workarounds.h | 3 +- drivers/gpu/drm/i915/gt/intel_workarounds_types.h | 3 +- drivers/gpu/drm/i915/gt/mock_engine.c | 29 +--- drivers/gpu/drm/i915/gt/mock_engine.h | 21 +-- drivers/gpu/drm/i915/gt/selftest_context.c | 3 +- drivers/gpu/drm/i915/gt/selftest_engine.c | 3 +- drivers/gpu/drm/i915/gt/selftest_engine.h | 3 +- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 3 +- .../gpu/drm/i915/gt/selftest_engine_heartbeat.c | 17 ++- drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 11 +- drivers/gpu/drm/i915/gt/selftest_execlists.c | 54 +++----- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 4 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 21 +-- drivers/gpu/drm/i915/gt/selftest_llc.c | 3 +- drivers/gpu/drm/i915/gt/selftest_llc.h | 3 +- drivers/gpu/drm/i915/gt/selftest_lrc.c | 1 - drivers/gpu/drm/i915/gt/selftest_mocs.c | 35 +++-- drivers/gpu/drm/i915/gt/selftest_rc6.c | 3 +- drivers/gpu/drm/i915/gt/selftest_rc6.h | 3 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 3 +- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 19 ++- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 +-- drivers/gpu/drm/i915/i915_buddy.c | 3 + drivers/gpu/drm/i915/i915_buddy.h | 7 +- drivers/gpu/drm/i915/i915_drv.c | 6 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/i915_priolist_types.h | 11 +- drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/i915_request.c | 9 +- drivers/gpu/drm/i915/i915_request.h | 2 +- drivers/gpu/drm/i915/i915_scheduler.c | 52 +------- drivers/gpu/drm/i915/i915_scheduler.h | 16 +-- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_device_info.h | 3 +- drivers/gpu/drm/i915/intel_memory_region.c | 54 +++++--- drivers/gpu/drm/i915/intel_memory_region.h | 22 ++-- drivers/gpu/drm/i915/selftests/i915_buddy.c | 48 +++++++ .../gpu/drm/i915/selftests/intel_memory_region.c | 77 +++++++++++ 115 files changed, 735 insertions(+), 844 deletions(-)

1 0

[PATCH] drm/i915/sysfs: convert snprintf to sysfs_emit
by Carlis 06 Apr '21

06 Apr '21

From: Xuezhi Zhang <zhangxuezhi1(a)yulong.com> Fix the following coccicheck warning: drivers/gpu/drm/i915//i915_sysfs.c:266:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:285:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:276:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:335:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:390:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:465:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:107:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:75:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:83:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:91:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:99:8-16: WARNING: use scnprintf or sprintf drivers/gpu/drm/i915//i915_sysfs.c:326:8-16: WARNING: use scnprintf or sprintf Signed-off-by: Xuezhi Zhang <zhangxuezhi1(a)yulong.com> --- drivers/gpu/drm/i915/i915_sysfs.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 45d32ef42787..4c6b5d52b5ca 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -72,7 +72,7 @@ show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf) if (HAS_RC6pp(dev_priv)) mask |= BIT(2); - return snprintf(buf, PAGE_SIZE, "%x\n", mask); + return sysfs_emit(buf, "%x\n", mask); } static ssize_t @@ -80,7 +80,7 @@ show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); + return sysfs_emit(buf, "%u\n", rc6_residency); } static ssize_t @@ -88,7 +88,7 @@ show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); + return sysfs_emit(buf, "%u\n", rc6p_residency); } static ssize_t @@ -96,7 +96,7 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); + return sysfs_emit(buf, "%u\n", rc6pp_residency); } static ssize_t @@ -104,7 +104,7 @@ show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6); - return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency); + return sysfs_emit(buf, "%u\n", rc6_residency); } static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL); @@ -263,8 +263,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev, struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); struct intel_rps *rps = &i915->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_rps_read_actual_frequency(rps)); + return sysfs_emit(buf, "%d\n", intel_rps_read_actual_frequency(rps)); } static ssize_t gt_cur_freq_mhz_show(struct device *kdev, @@ -273,8 +272,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); struct intel_rps *rps = &i915->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->cur_freq)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->cur_freq)); } static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) @@ -282,8 +280,7 @@ static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribu struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); struct intel_rps *rps = &i915->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->boost_freq)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->boost_freq)); } static ssize_t gt_boost_freq_mhz_store(struct device *kdev, @@ -323,8 +320,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); struct intel_rps *rps = &dev_priv->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->efficient_freq)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->efficient_freq)); } static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) @@ -332,8 +328,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); struct intel_rps *rps = &dev_priv->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->max_freq_softlimit)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->max_freq_softlimit)); } static ssize_t gt_max_freq_mhz_store(struct device *kdev, @@ -387,8 +382,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); struct intel_rps *rps = &dev_priv->gt.rps; - return snprintf(buf, PAGE_SIZE, "%d\n", - intel_gpu_freq(rps, rps->min_freq_softlimit)); + return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->min_freq_softlimit)); } static ssize_t gt_min_freq_mhz_store(struct device *kdev, @@ -462,7 +456,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr else BUG(); - return snprintf(buf, PAGE_SIZE, "%d\n", val); + return sysfs_emit(buf, "%d\n", val); } static const struct attribute * const gen6_attrs[] = { -- 2.25.1

2 1

[PATCH v1] drm/bridge/sii8620: fix dependency on extcon
by Robert Foss 06 Apr '21

06 Apr '21

The DRM_SIL_SII8620 kconfig has a weak `imply` dependency on EXTCON, which causes issues when sii8620 is built as a builtin and EXTCON is built as a module. Th symptoms are 'undefined reference' errors caused by the symbols in EXTCON not being available to the sii8620 driver. Signed-off-by: Robert Foss <robert.foss(a)linaro.org> Reported-by: kernel test robot <lkp(a)intel.com> --- LKP reported issue: https://lore.kernel.org/lkml/202104040604.SSTe2Cxf-lkp@intel.com/ drivers/gpu/drm/bridge/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 7c15fc170510..204c38e87849 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -169,7 +169,7 @@ config DRM_SIL_SII8620 tristate "Silicon Image SII8620 HDMI/MHL bridge" depends on OF select DRM_KMS_HELPER - imply EXTCON + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in depends on RC_CORE || !RC_CORE help Silicon Image SII8620 HDMI/MHL bridge chip driver. -- 2.31.0.30.g398dba342d.dirty

1 0

[PATCH v2 0/1] drm/nouveau/dmem: Remove duplicated header file
by Zhen Lei 06 Apr '21

06 Apr '21

v1 --> v2: Arrange all included header files in alphabetical order. Zhen Lei (1): drm/nouveau/dmem: Remove duplicated header file inclusion drivers/gpu/drm/nouveau/nouveau_dmem.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) -- 1.8.3

1 1

[PATCH -next] backlight: backlight: Use DEFINE_MUTEX() for mutex lock
by Zheng Yongjun 06 Apr '21

06 Apr '21

mutex lock can be initialized automatically with DEFINE_MUTEX() rather than explicitly calling mutex_init(). Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Zheng Yongjun <zhengyongjun3(a)huawei.com> --- drivers/video/backlight/backlight.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c index 537fe1b376ad..d7a09c422547 100644 --- a/drivers/video/backlight/backlight.c +++ b/drivers/video/backlight/backlight.c @@ -64,7 +64,7 @@ */ static struct list_head backlight_dev_list; -static struct mutex backlight_dev_list_mutex; +static DEFINE_MUTEX(backlight_dev_list_mutex); static struct blocking_notifier_head backlight_notifier; static const char *const backlight_types[] = { @@ -757,7 +757,6 @@ static int __init backlight_class_init(void) backlight_class->dev_groups = bl_device_groups; backlight_class->pm = &backlight_class_dev_pm_ops; INIT_LIST_HEAD(&backlight_dev_list); - mutex_init(&backlight_dev_list_mutex); BLOCKING_INIT_NOTIFIER_HEAD(&backlight_notifier); return 0;

2 1

[Bug 200695] New: Blank screen on RX 580 with amdgpu.dc=1 enabled (no displays detected)
by bugzilla-daemon＠bugzilla.kernel.org 06 Apr '21

06 Apr '21

https://bugzilla.kernel.org/show_bug.cgi?id=200695 Bug ID: 200695 Summary: Blank screen on RX 580 with amdgpu.dc=1 enabled (no displays detected) Product: Drivers Version: 2.5 Kernel Version: 4.18.0-rc7 Hardware: All OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: claude(a)mathr.co.uk Regression: No Created attachment 277633 --> https://bugzilla.kernel.org/attachment.cgi?id=277633&action=edit dmesg after boot with amdgpu.dc=1 amdgpu.dc_log=1 drm.debug=6 When amdgpu.dc=1 is initialized at boot, the console goes blank as it thinks all displays are disconnected. Xorg is not able to enable the display either. With amdgpu.dc=0 all is fine. Tried with various (mostly Debian) kernels from 4.16 through 4.18~rc4, all have the issue. I built a 4.18~rc7 from kernel.org to rule out Debian patches being the issue and will provide logs. -- You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH v1 0/3] Add irq support to accommodate SC7280 target
by Krishna Manikandan 06 Apr '21

06 Apr '21

The changes in this series adds all the irq related changes which are needed to support EDP interface coming on sc7280 target. Changes in this series: - Currently each interrupt register has a range of 32 indexes only. But with the introduction of VSYNC and UNDERRUN irq for INTF_5, the number of irqs under INTR_STATUS will exceed this value. Increase the range of each interrupt register to 64 indexes to handle this. - Changes are added to enable the vsync and underrun irqs for INTF_5 which is required for edp panel. - Some irqs which are applicable for sdm845 target are obsolete for sc7180 and sc7280 targets. Support is added to skip all the obsolete irqs based on the target. Krishna Manikandan (3): drm/msm/disp/dpu1: increase the range of interrupts in dpu_irq_map drm/msm/disp/dpu1: add vsync and underrun irqs for INTF_5 drm/msm/disp/dpu1: add flags to indicate obsolete irqs drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 773 +++++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 5 +- 5 files changed, 692 insertions(+), 101 deletions(-) -- 2.7.4

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linux-next: manual merge of the imx-drm tree with the drm tree
by Stephen Rothwell 06 Apr '21

06 Apr '21

Hi all, Today's linux-next merge of the imx-drm tree got a conflict in: drivers/gpu/drm/imx/ipuv3-plane.c between commits: ba5c1649465d ("drm: Rename plane atomic_check state names") 41016fe1028e ("drm: Rename plane->state variables in atomic update and disable") from the drm tree and commit: 49c826e1941a ("drm/imx: Add 8 pixel alignment fix") from the imx-drm tree. I fixed it up (see below) and can carry the fix as necessary. This is now fixed as far as linux-next is concerned, but any non trivial conflicts should be mentioned to your upstream maintainer when your tree is submitted for merging. You may also want to consider cooperating with the maintainer of the conflicting tree to minimise any particularly complex conflicts. -- Cheers, Stephen Rothwell diff --cc drivers/gpu/drm/imx/ipuv3-plane.c index fa5009705365,26f2cc832101..000000000000 --- a/drivers/gpu/drm/imx/ipuv3-plane.c +++ b/drivers/gpu/drm/imx/ipuv3-plane.c @@@ -590,8 -618,8 +625,8 @@@ static void ipu_plane_atomic_update(str if (ipu_state->use_pre) { axi_id = ipu_chan_assign_axi_id(ipu_plane->dma); ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id, - drm_rect_width(&new_state->src) >> 16, - ipu_src_rect_width(state), - drm_rect_height(&state->src) >> 16, ++ ipu_src_rect_width(new_state), + drm_rect_height(&new_state->src) >> 16, fb->pitches[0], fb->format->format, fb->modifier, &eba); } @@@ -623,10 -651,10 +658,10 @@@ break; } - ipu_dmfc_config_wait4eot(ipu_plane->dmfc, drm_rect_width(dst)); + ipu_dmfc_config_wait4eot(ipu_plane->dmfc, ALIGN(drm_rect_width(dst), 8)); - width = drm_rect_width(&new_state->src) >> 16; - width = ipu_src_rect_width(state); - height = drm_rect_height(&state->src) >> 16; ++ width = ipu_src_rect_width(new_state); + height = drm_rect_height(&new_state->src) >> 16; info = drm_format_info(fb->format->format); ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0], &burstsize, &num_bursts); @@@ -690,8 -717,8 +725,8 @@@ ipu_cpmem_zero(ipu_plane->alpha_ch); ipu_cpmem_set_resolution(ipu_plane->alpha_ch, - drm_rect_width(&new_state->src) >> 16, - ipu_src_rect_width(state), - drm_rect_height(&state->src) >> 16); ++ ipu_src_rect_width(new_state), + drm_rect_height(&new_state->src) >> 16); ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8); ipu_cpmem_set_high_priority(ipu_plane->alpha_ch); ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);

1 0

[PATCH v1 0/4] Add display support for SC7280 target
by Krishna Manikandan 06 Apr '21

06 Apr '21

The changes in this series adds all the required support for display driver for SC7280 target. In addition to the basic catalog changes, changes are added to accommodate new registers for SC7280 target. SC7280 target comes under next generation targets. The register differences in SC7280 when compared to SC7180 are mentioned below: - SC7280 uses UBWC3.0 and changes are added to program the ubwc static registers properly - Pingpong dither block offset value has changed for SC7280 family. Separate sub block is defined for sc7280 pingpong block and changes are added to handle this. - Interface offsets are different for SC7280 family. These offset values are used to access the interface irq registers. Changes are added to handle this based on the target. - A new register called CTL_FETCH_PIPE_ACTIVE is introduced in SC7280 family, which tells the HW about the active pipes in the CTL path. Changes are added to program this register based on the active pipes in the current composition. - Changes are added to program INTF_CONFIG2 properly since the reset value of this register has changed in SC7280 family and we need to explicitly program it with correct values to avoid wrong interface configuration. - INTF_5 is added to intf configuration to support EDP. Krishna Manikandan (4): drm/msm/disp/dpu1: add support for display for SC7280 target drm/msm/disp/dpu1: add intf offsets for SC7280 target drm/msm/disp/dpu1: add support to program fetch active in ctl path drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 176 ++++++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 27 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 20 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 11 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 6 +- drivers/gpu/drm/msm/msm_drv.c | 4 +- 10 files changed, 242 insertions(+), 24 deletions(-) -- 2.7.4

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dri-devel April 2021