dri-devel August 2021

dri-devel@lists.freedesktop.org

324 participants
762 discussions

[PATCH v2] drm/mediatek: add AAL output size configuration
by jason-jh.lin 11 Aug '21

11 Aug '21

To avoid the output width and height is incorrect, AAL_OUTPUT_SIZE configuration should be set. Fixes: 0664d1392c26 ("drm/mediatek: Add AAL engine basic function") Signed-off-by: jason-jh.lin <jason-jh.lin(a)mediatek.com> --- Change in v2: - fix to one line --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 75bc00e17fc4..50d20562e612 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -34,6 +34,7 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030 +#define DISP_AAL_OUTPUT_SIZE 0x04d8 #define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) @@ -197,6 +198,7 @@ static void mtk_aal_config(struct device *dev, unsigned int w, struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_OUTPUT_SIZE); } static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) -- 2.18.0

2 1

[PATCH v2 0/6] drm/bridge: ti-sn65dsi86: Misc improvements
by Laurent Pinchart 11 Aug '21

11 Aug '21

Hello, This patch series contains miscellaneous improvements to the ti-sn65dsi86 driver, and prepares it for optional connector creation and DisplayPort (non-eDP) support. The patches have been posted previously as part of the "[RFC PATCH 00/11] drm/bridge: ti-sn65dsi86: Support DisplayPort mode" series. The last four patches have been left out as discussions are ongoing, this series focusses on the base work that has mostly been approved during the review of the RFC. The code has been rebased on top of the latest drm-misc-next, and while some changes to the ti-sn65dsi86 driver made conflict resolution painful in patch 5/6, there was no big functional conflict. Laurent Pinchart (6): dt-bindings: drm/bridge: ti-sn65dsi8: Make enable GPIO optional drm/bridge: ti-sn65dsi86: Make enable GPIO optional drm/bridge: ti-sn65dsi86: Use bitmask to store valid rates drm/bridge: ti-sn65dsi86: Wrap panel with panel-bridge drm/bridge: ti-sn65dsi86: Group code in sections drm/bridge: ti-sn65dsi86: Split connector creation to a function .../bindings/display/bridge/ti,sn65dsi86.yaml | 1 - drivers/gpu/drm/bridge/ti-sn65dsi86.c | 703 ++++++++++-------- 2 files changed, 374 insertions(+), 330 deletions(-) base-commit: 7601d53c2c49e3a7e8150e8cf332b3c17943f75a -- Regards, Laurent Pinchart

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[PATCH v4 00/14] Provide core infrastructure for managing open/release
by Jason Gunthorpe 11 Aug '21

11 Aug '21

This is in support of Max's series to split vfio-pci. For that to work the reflck concept embedded in vfio-pci needs to be sharable across all of the new VFIO PCI drivers which motivated re-examining how this is implemented. Another significant issue is how the VFIO PCI core includes code like: if (pci_dev_driver(pdev) != &vfio_pci_driver) Which is not scalable if there are going to be multiple different driver types. This series takes the approach of moving the "reflck" mechanism into the core code as a "device set". Each vfio_device driver can specify how vfio_devices are grouped into the set using a key and the set comes along with a set-global mutex. The core code manages creating per-device set memory and associating it with each vfio_device. In turn this allows the core code to provide an open/close_device() operation that is called only for the first/last FD, and is called under the global device set lock. Review of all the drivers show that they are either already open coding the first/last semantic or are buggy and missing it. All drivers are migrated/fixed to the new open/close_device ops and the unused per-FD open()/release() ops are deleted. The special behavior of PCI around the bus/slot "reset group" is recast in terms of the device set which conslidates the reflck, eliminates two touches of pci_dev_driver(), and allows the reset mechanism to share across all VFIO PCI drivers. PCI is changed to acquire devices directly from the device set instead of trying to work backwards from the struct pci_device. Overall a few minor bugs are squashed and quite a bit of code is removed through consolidation. v4: - Fix use-after-free typo in mbochs error unwind - Allow mdevs to work when they don't have open/release ops, for bisect-ability - Redo the vfio_pci_try_bus_reset() patch, make it dev_set centric - Change VFIO_DEVICE_PCI_HOT_RESET to align with the new vfio_pci_try_bus_reset() design v3: https://lore.kernel.org/r/0-v3-6c9e19cc7d44+15613-vfio_reflck_jgg@nvidia.com - Atomic conversion of mbochs_used_mbytes - Add missing vfio_uninit_group_dev in error unwind of mbochs - Reorganize vfio_assign_device_set() - Move the dev_set_list hunks to the introduction of the dev_set - Use if instead of ?: in fsl - Add a comment about the whole bus reset in vfio_pci_probe() - Rename vfio_pci_check_all_devices_bound() to vfio_pci_is_device_in_set() - Move logic from vfio_pci_try_bus_reset() into vfio_pci_find_reset_target() v2: https://lore.kernel.org/r/0-v2-b6a5582525c9+ff96-vfio_reflck_jgg@nvidia.com - Reorder fsl and mbochs vfio_uninit_group_dev - Fix missing error unwind in mbochs - Return 0 from mdev open_device if there is no op - Fix style for else {} - Spelling fix for singleton - Acquire cur_mem under lock - Always use error unwind flow for vfio_pci_check_all_devices_bound() v1: https://lore.kernel.org/r/0-v1-eaf3ccbba33c+1add0-vfio_reflck_jgg@nvidia.com Jason Gunthorpe (12): vfio/samples: Remove module get/put vfio/mbochs: Fix missing error unwind of mbochs_used_mbytes vfio: Provide better generic support for open/release vfio_device_ops vfio/samples: Delete useless open/close vfio/fsl: Move to the device set infrastructure vfio/platform: Use open_device() instead of open coding a refcnt scheme vfio/pci: Change vfio_pci_try_bus_reset() to use the dev_set vfio/pci: Reorganize VFIO_DEVICE_PCI_HOT_RESET to use the device set vfio/mbochs: Fix close when multiple device FDs are open vfio/ap,ccw: Fix open/close when multiple device FDs are open vfio/gvt: Fix open/close when multiple device FDs are open vfio: Remove struct vfio_device_ops open/release Max Gurtovoy (1): vfio: Introduce a vfio_uninit_group_dev() API call Yishai Hadas (1): vfio/pci: Move to the device set infrastructure Documentation/driver-api/vfio.rst | 4 +- drivers/gpu/drm/i915/gvt/kvmgt.c | 8 +- drivers/s390/cio/vfio_ccw_ops.c | 8 +- drivers/s390/crypto/vfio_ap_ops.c | 8 +- drivers/vfio/fsl-mc/vfio_fsl_mc.c | 161 +----- drivers/vfio/fsl-mc/vfio_fsl_mc_intr.c | 6 +- drivers/vfio/fsl-mc/vfio_fsl_mc_private.h | 7 - drivers/vfio/mdev/vfio_mdev.c | 33 +- drivers/vfio/pci/vfio_pci.c | 539 +++++++----------- drivers/vfio/pci/vfio_pci_private.h | 7 - drivers/vfio/platform/vfio_platform_common.c | 102 ++-- drivers/vfio/platform/vfio_platform_private.h | 1 - drivers/vfio/vfio.c | 142 ++++- include/linux/mdev.h | 9 +- include/linux/vfio.h | 26 +- samples/vfio-mdev/mbochs.c | 40 +- samples/vfio-mdev/mdpy.c | 40 +- samples/vfio-mdev/mtty.c | 40 +- 18 files changed, 509 insertions(+), 672 deletions(-) base-commit: 3fb1712d85962f81265b5018922a2da13cdf6033 -- 2.32.0

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[PATCH] gpu: drm: amd: amdgpu: amdgpu_i2c: fix possible uninitialized-variable access in amdgpu_i2c_router_select_ddc_port()
by Tuo Li 11 Aug '21

11 Aug '21

The variable val is declared without initialization, and its address is passed to amdgpu_i2c_get_byte(). In this function, the value of val is accessed in: DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", addr, *val); Also, when amdgpu_i2c_get_byte() returns, val may remain uninitialized, but it is accessed in: val &= ~amdgpu_connector->router.ddc_mux_control_pin; To fix this possible uninitialized-variable access, initialize val to 0 in amdgpu_i2c_router_select_ddc_port(). Reported-by: TOTE Robot <oslab(a)tsinghua.edu.cn> Signed-off-by: Tuo Li <islituo(a)gmail.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c index bca4dddd5a15..82608df43396 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c @@ -339,7 +339,7 @@ static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, void amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector) { - u8 val; + u8 val = 0; if (!amdgpu_connector->router.ddc_valid) return; -- 2.25.1

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[Intel-gfx] [PATCH v3 0/3] drm/i915/hdcp: HDCP2.2 MST dock fixes
by Juston Li 11 Aug '21

11 Aug '21

Fixes to get HDCP2.2 over MST working on MST docking stations with certain behaviors that cause the current flow to fail. Tested with Dell WD-19 and Lenovo ThinkPad USB Type-C Dock Gen 2. These fixes should make the flow more robust to handle behaviors that as far as I can tell are unclear in the HDCP spec: RxInfo contains repeater topology information needed for MST. The behavior on these docks is that this can only be read during RepeaterAuth_Send_ReceiverID_List when the RxStatus READY bit is set otherwise the dock will return NACK. It seems these docks treat reading this range at any other time as invalid when the READY bit isn't set possibly because it could be stale. The HDCP spec also states the READY bit is cleared after RxInfo is read. These fixes address this behavior by only reading RxInfo once during the AKE flow and reusing that data. Changes since v2: - Remove no longer used variables in _intel_hdcp2_enable() Changes since v1: - Fix subject line for 3/3 Juston Li (3): drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg() drm/i915/hdcp: read RxInfo once when reading RepeaterAuth_Send_ReceiverID_List drm/i915/hdcp: reuse rx_info for mst stream type1 capability check .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 77 +++++-------------- drivers/gpu/drm/i915/display/intel_hdcp.c | 49 +++++------- include/drm/drm_dp_helper.h | 2 +- 4 files changed, 43 insertions(+), 87 deletions(-) -- 2.31.1

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[PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support
by Akhil P Oommen 11 Aug '21

11 Aug '21

Add the necessary dt nodes for gpu support in sc7280. Signed-off-by: Akhil P Oommen <akhilpo(a)codeaurora.org> --- Changes in v5: - Added Stephen's reviewed-by tag to patch-2 Changes in v4: - Removed the dependency on gpucc bindings (Stephen) - Reordered GPU's opp table Changes in v3: - Re-ordered the nodes based on address (Stephen) - Added the patch for gpu cooling to the stack. Changes in v2: - formatting update and removed a duplicate header (Stephen) arch/arm64/boot/dts/qcom/sc7280.dtsi | 115 +++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 029723a..b9006d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -592,6 +592,85 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + gpu@3d00000 { + compatible = "qcom,adreno-635.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0 0x401>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <1804000>; + }; + + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <4068000>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <6832000>; + }; + }; + }; + + gmu: gmu@3d69000 { + compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x34000>, + <0 0x3de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc 5>, + <&gpucc 8>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc 2>, + <&gpucc 15>, + <&gpucc 11>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains = <&gpucc 0>, + <&gpucc 1>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0x400>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sc7280-gpucc"; reg = <0 0x03d90000 0 0x9000>; @@ -606,6 +685,42 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc 2>, + <&gpucc 11>, + <&gpucc 5>, + <&gpucc 15>, + <&gpucc 13>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + power-domains = <&gpucc 0>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation.

2 2

[PATCH v2 0/6] drm/ingenic: Various improvements v2
by Paul Cercueil 11 Aug '21

11 Aug '21

Hi, A V2 of my patchset for the ingenic-drm driver. The patches "drm/ingenic: Remove dead code" and "drm/ingenic: Use standard drm_atomic_helper_commit_tail" that were present in V1 have been merged in drm-misc-next, so they are not in this V2. Changelog: [PATCH 1/6]: dma_hwdesc_addr() extended to support palette hwdesc. The palette hwdesc is now hwdesc[3] to simplify things. Add ingenic_drm_configure_hwdesc*() functions to factorize code. Cheers, -Paul Paul Cercueil (6): drm/ingenic: Simplify code by using hwdescs array drm/ingenic: Add support for private objects drm/ingenic: Move IPU scale settings to private state drm/ingenic: Set DMA descriptor chain register when starting CRTC drm/ingenic: Upload palette before frame drm/ingenic: Attach bridge chain to encoders drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 278 +++++++++++++++++----- drivers/gpu/drm/ingenic/ingenic-ipu.c | 127 ++++++++-- 2 files changed, 333 insertions(+), 72 deletions(-) -- 2.30.2

1 6

[PATCH] video: fbdev: w100fb: Reset global state
by Evgeny Novikov 11 Aug '21

11 Aug '21

w100fb_probe() did not reset the global state to its initial state. This can result in invocation of iounmap() even when there was not the appropriate successful call of ioremap(). For instance, this may be the case if first probe fails after two successful ioremap() while second probe fails when first ioremap() fails. The similar issue is with w100fb_remove(). The patch fixes both bugs. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Evgeny Novikov <novikov(a)ispras.ru> Co-developed-by: Kirill Shilimanov <kirill.shilimanov(a)huawei.com> Signed-off-by: Kirill Shilimanov <kirill.shilimanov(a)huawei.com> --- drivers/video/fbdev/w100fb.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/video/fbdev/w100fb.c b/drivers/video/fbdev/w100fb.c index d96ab28f8ce4..4e641a780726 100644 --- a/drivers/video/fbdev/w100fb.c +++ b/drivers/video/fbdev/w100fb.c @@ -770,12 +770,18 @@ static int w100fb_probe(struct platform_device *pdev) fb_dealloc_cmap(&info->cmap); kfree(info->pseudo_palette); } - if (remapped_fbuf != NULL) + if (remapped_fbuf != NULL) { iounmap(remapped_fbuf); - if (remapped_regs != NULL) + remapped_fbuf = NULL; + } + if (remapped_regs != NULL) { iounmap(remapped_regs); - if (remapped_base != NULL) + remapped_regs = NULL; + } + if (remapped_base != NULL) { iounmap(remapped_base); + remapped_base = NULL; + } if (info) framebuffer_release(info); return err; @@ -795,8 +801,11 @@ static int w100fb_remove(struct platform_device *pdev) fb_dealloc_cmap(&info->cmap); iounmap(remapped_base); + remapped_base = NULL; iounmap(remapped_regs); + remapped_regs = NULL; iounmap(remapped_fbuf); + remapped_fbuf = NULL; framebuffer_release(info); -- 2.26.2

1 0

[PATCH v6 0/7] Add Mediatek Soc DRM (vdosys0) support for mt8195
by jason-jh.lin 11 Aug '21

11 Aug '21

The hardware path of vdosys0 with eDP panel output need to go through by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA, DITHER, DSC and MERGE. Change in v6: - adjust alphabetic order for mediatek-drm - move the patch that add mt8195 support for mediatek-drm as the lastest patch - add MERGE define for const varriable Change in v5: - add power-domain property into vdosys0 and vdosys1 dts node. - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h Change in v4: - extract dt-binding patches to another patch series https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597 - squash DSC module into mtk_drm_ddp_comp.c - add coment and simplify MERGE config function Change in v3: - change mmsys and display dt-bindings document from txt to yaml - add MERGE additional description in display dt-bindings document - fix mboxes-cells number of vdosys0 node in dts - drop mutex eof convert define - remove pm_runtime apis in DSC and MERGE - change DSC and MERGE enum to alphabetic order Change in v2: - add DSC yaml file - add mt8195 drm driver porting parts in to one patch - remove useless define, variable, structure member and function - simplify DSC and MERGE file and switch threre order jason-jh.lin (7): arm64: dts: mt8195: add display node for vdosys0 soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 soc: mediatek: add mtk-mutex support for mt8195 vdosys0 drm/mediatek: adjust to the alphabetic order for mediatek-drm drm/mediatek: add DSC support for mediatek-drm drm/mediatek: add MERGE support for mediatek-drm drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 112 +++++++++ drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 + drivers/gpu/drm/mediatek/mtk_disp_merge.c | 263 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 242 +++++++++++------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 24 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 108 +++++--- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mt8195-mmsys.h | 96 +++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 + drivers/soc/mediatek/mtk-mutex.c | 93 ++++++- include/linux/soc/mediatek/mtk-mmsys.h | 9 + 13 files changed, 825 insertions(+), 149 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h -- 2.18.0

4 16

linux-next: Signed-off-by missing for commit in the drm-intel tree
by Stephen Rothwell 11 Aug '21

11 Aug '21

Hi all, Commit db47fe727e1f ("drm/i915/step: s/<platform>_revid_tbl/<platform>_revids") is missing a Signed-off-by from its committer. -- Cheers, Stephen Rothwell

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dri-devel August 2021