dri-devel January 2022

dri-devel@lists.freedesktop.org

373 participants
842 discussions

[PATCH 0/3] Flush G2H handler during a GT reset
by Matthew Brost 21 Jan '22

21 Jan '22

After a small fix to error capture code, we now can flush G2H during a GT reset which simplifies code and seals some extreme corner case races. v2: (CI) - Don't trigger GT reset from G2H handler v3: - Address John Harrison's comments Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> Matthew Brost (3): drm/i915: Allocate intel_engine_coredump_alloc with ALLOW_FAIL drm/i915/guc: Add work queue to trigger a GT reset drm/i915/guc: Flush G2H handler during a GT reset drivers/gpu/drm/i915/gt/uc/intel_guc.h | 9 +++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 55 ++++++++++++------- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 3 files changed, 44 insertions(+), 22 deletions(-) -- 2.34.1

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[PATCH v1, 0/1] soc: mediatek: cmdq: add cmdq_pkt_poll_addr function
by Yongqiang Niu 21 Jan '22

21 Jan '22

add cmdq_pkt_poll_addr function mtk18742 (1): soc: mediatek: cmdq: add cmdq_pkt_poll_addr function drivers/soc/mediatek/mtk-cmdq-helper.c | 39 ++++++++++++++++++++++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 1 + include/linux/soc/mediatek/mtk-cmdq.h | 2 ++ 3 files changed, 42 insertions(+) -- 2.25.1

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[syzbot] KASAN: vmalloc-out-of-bounds Write in imageblit (2)
by syzbot 21 Jan '22

21 Jan '22

Hello, syzbot found the following issue on: HEAD commit: fa55b7dcdc43 Linux 5.16-rc1 git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?x=15fe2569b00000 kernel config: https://syzkaller.appspot.com/x/.config?x=6d3b8fd1977c1e73 dashboard link: https://syzkaller.appspot.com/bug?extid=14b0e8f3fd1612e35350 compiler: gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2 userspace arch: i386 Unfortunately, I don't have any reproducer for this issue yet. IMPORTANT: if you fix the issue, please add the following tag to the commit: Reported-by: syzbot+14b0e8f3fd1612e35350(a)syzkaller.appspotmail.com 524155 pages RAM 0 pages HighMem/MovableOnly 163742 pages reserved 0 pages cma reserved ================================================================== BUG: KASAN: vmalloc-out-of-bounds in fast_imageblit drivers/video/fbdev/core/sysimgblt.c:229 [inline] BUG: KASAN: vmalloc-out-of-bounds in sys_imageblit+0x12f4/0x1430 drivers/video/fbdev/core/sysimgblt.c:275 Write of size 4 at addr ffffc90004631000 by task syz-executor.0/7913 CPU: 0 PID: 7913 Comm: syz-executor.0 Not tainted 5.16.0-rc1-syzkaller #0 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.14.0-2 04/01/2014 Call Trace: <TASK> __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0xcd/0x134 lib/dump_stack.c:106 print_address_description.constprop.0.cold+0xf/0x320 mm/kasan/report.c:247 __kasan_report mm/kasan/report.c:433 [inline] kasan_report.cold+0x83/0xdf mm/kasan/report.c:450 fast_imageblit drivers/video/fbdev/core/sysimgblt.c:229 [inline] sys_imageblit+0x12f4/0x1430 drivers/video/fbdev/core/sysimgblt.c:275 drm_fb_helper_sys_imageblit drivers/gpu/drm/drm_fb_helper.c:794 [inline] drm_fbdev_fb_imageblit+0x15c/0x350 drivers/gpu/drm/drm_fb_helper.c:2282 bit_putcs_unaligned drivers/video/fbdev/core/bitblit.c:124 [inline] bit_putcs+0x6e1/0xd20 drivers/video/fbdev/core/bitblit.c:173 fbcon_putcs+0x353/0x440 drivers/video/fbdev/core/fbcon.c:1277 do_update_region+0x399/0x630 drivers/tty/vt/vt.c:676 redraw_screen+0x61f/0x740 drivers/tty/vt/vt.c:1035 fbcon_modechanged+0x58c/0x6c0 drivers/video/fbdev/core/fbcon.c:2182 fbcon_update_vcs+0x3a/0x50 drivers/video/fbdev/core/fbcon.c:2227 do_fb_ioctl+0x62e/0x690 drivers/video/fbdev/core/fbmem.c:1114 fb_compat_ioctl+0x17e/0x610 drivers/video/fbdev/core/fbmem.c:1313 __do_compat_sys_ioctl+0x1c7/0x290 fs/ioctl.c:972 do_syscall_32_irqs_on arch/x86/entry/common.c:112 [inline] __do_fast_syscall_32+0x65/0xf0 arch/x86/entry/common.c:178 do_fast_syscall_32+0x2f/0x70 arch/x86/entry/common.c:203 entry_SYSENTER_compat_after_hwframe+0x4d/0x5c RIP: 0023:0xf6e67549 Code: 03 74 c0 01 10 05 03 74 b8 01 10 06 03 74 b4 01 10 07 03 74 b0 01 10 08 03 74 d8 01 00 00 00 00 00 51 52 55 89 e5 0f 34 cd 80 <5d> 5a 59 c3 90 90 90 90 8d b4 26 00 00 00 00 8d b4 26 00 00 00 00 RSP: 002b:00000000f44615fc EFLAGS: 00000296 ORIG_RAX: 0000000000000036 RAX: ffffffffffffffda RBX: 0000000000000005 RCX: 0000000000004601 RDX: 0000000020000000 RSI: 0000000000000000 RDI: 0000000000000000 RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 </TASK> Memory state around the buggy address: ffffc90004630f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ffffc90004630f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >ffffc90004631000: f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 ^ ffffc90004631080: f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 ffffc90004631100: f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 ================================================================== ---------------- Code disassembly (best guess): 0: 03 74 c0 01 add 0x1(%rax,%rax,8),%esi 4: 10 05 03 74 b8 01 adc %al,0x1b87403(%rip) # 0x1b8740d a: 10 06 adc %al,(%rsi) c: 03 74 b4 01 add 0x1(%rsp,%rsi,4),%esi 10: 10 07 adc %al,(%rdi) 12: 03 74 b0 01 add 0x1(%rax,%rsi,4),%esi 16: 10 08 adc %cl,(%rax) 18: 03 74 d8 01 add 0x1(%rax,%rbx,8),%esi 1c: 00 00 add %al,(%rax) 1e: 00 00 add %al,(%rax) 20: 00 51 52 add %dl,0x52(%rcx) 23: 55 push %rbp 24: 89 e5 mov %esp,%ebp 26: 0f 34 sysenter 28: cd 80 int $0x80 * 2a: 5d pop %rbp <-- trapping instruction 2b: 5a pop %rdx 2c: 59 pop %rcx 2d: c3 retq 2e: 90 nop 2f: 90 nop 30: 90 nop 31: 90 nop 32: 8d b4 26 00 00 00 00 lea 0x0(%rsi,%riz,1),%esi 39: 8d b4 26 00 00 00 00 lea 0x0(%rsi,%riz,1),%esi --- This report is generated by a bot. It may contain errors. See https://goo.gl/tpsmEJ for more information about syzbot. syzbot engineers can be reached at syzkaller(a)googlegroups.com. syzbot will keep track of this issue. See: https://goo.gl/tpsmEJ#status for how to communicate with syzbot.

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[RFC 00/10] drm: selftests: Convert to KUnit
by Michał Winiarski 21 Jan '22

21 Jan '22

KUnit unifies the test structure and provides helper tools that simplify the development. Basic use case allows running tests as regular processes, leveraging User Mode Linux. For example, to execute all DRM unit tests: ./tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm (the tool also allows using QEMU instead of UML by adding e.g. --arch=x86_64) For developers - it means that it's easier to run unit tests on the development machine, tightening the feedback loop. When using UML, it also simplifies using gdb for debug (since the kernel is just a regular process). For CI systems - DRM tests can be moved from being executed on device under test (that's also running IGTs and so on) to being executed on buildsystem during build (just like checkpatch.pl). All tests were renamed - IGT prefix is no longer used. Compared to selftests executed by CI using IGT, there's one functional regression - KUnit test runner is not catching WARNs. To solve this, we could either go in the similar direction that UBSAN went in: 1195505 ("kunit: ubsan integration") Or we could expand the test runner to catch WARN signature in dmesg. Pastebin to preview the output and execution times: https://gitlab.freedesktop.org/-/snippets/4139 -Michał Michał Winiarski (10): drm: test-drm_cmdline_parser: Convert to KUnit drm: test-drm_plane_helper: Convert to KUnit drm: test-drm_format: Convert to KUnit drm: test-drm_framebuffer: Convert to KUnit drm: test-drm_damage_helper: Convert to KUnit drm: test-drm_dp_mst_helper: Convert to KUnit drm: test-drm_rect: Convert to KUnit drm: test-drm_mm: Convert to KUnit drm: selftests: Convert to KUnit drm: test: Simplify testing on UML with kunit.py drivers/gpu/drm/.kunitconfig | 3 + drivers/gpu/drm/Kconfig | 22 +- drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/i915/Kconfig.debug | 1 - drivers/gpu/drm/selftests/Makefile | 7 - .../gpu/drm/selftests/drm_cmdline_selftests.h | 68 - drivers/gpu/drm/selftests/drm_mm_selftests.h | 28 - .../gpu/drm/selftests/drm_modeset_selftests.h | 40 - drivers/gpu/drm/selftests/drm_selftest.c | 109 - drivers/gpu/drm/selftests/drm_selftest.h | 41 - .../drm/selftests/test-drm_cmdline_parser.c | 1141 -------- .../drm/selftests/test-drm_damage_helper.c | 667 ----- .../drm/selftests/test-drm_dp_mst_helper.c | 273 -- drivers/gpu/drm/selftests/test-drm_format.c | 280 -- drivers/gpu/drm/selftests/test-drm_mm.c | 2487 ----------------- .../drm/selftests/test-drm_modeset_common.c | 32 - .../drm/selftests/test-drm_modeset_common.h | 52 - .../gpu/drm/selftests/test-drm_plane_helper.c | 223 -- drivers/gpu/drm/selftests/test-drm_rect.c | 223 -- drivers/gpu/drm/test/Makefile | 7 + .../gpu/drm/test/test-drm_cmdline_parser.c | 1027 +++++++ drivers/gpu/drm/test/test-drm_damage_helper.c | 667 +++++ drivers/gpu/drm/test/test-drm_dp_mst_helper.c | 429 +++ drivers/gpu/drm/test/test-drm_format.c | 356 +++ .../test-drm_framebuffer.c | 109 +- drivers/gpu/drm/test/test-drm_mm.c | 2426 ++++++++++++++++ drivers/gpu/drm/test/test-drm_plane_helper.c | 312 +++ drivers/gpu/drm/test/test-drm_rect.c | 249 ++ drivers/video/Kconfig | 4 + 29 files changed, 5558 insertions(+), 5727 deletions(-) create mode 100644 drivers/gpu/drm/.kunitconfig delete mode 100644 drivers/gpu/drm/selftests/Makefile delete mode 100644 drivers/gpu/drm/selftests/drm_cmdline_selftests.h delete mode 100644 drivers/gpu/drm/selftests/drm_mm_selftests.h delete mode 100644 drivers/gpu/drm/selftests/drm_modeset_selftests.h delete mode 100644 drivers/gpu/drm/selftests/drm_selftest.c delete mode 100644 drivers/gpu/drm/selftests/drm_selftest.h delete mode 100644 drivers/gpu/drm/selftests/test-drm_cmdline_parser.c delete mode 100644 drivers/gpu/drm/selftests/test-drm_damage_helper.c delete mode 100644 drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c delete mode 100644 drivers/gpu/drm/selftests/test-drm_format.c delete mode 100644 drivers/gpu/drm/selftests/test-drm_mm.c delete mode 100644 drivers/gpu/drm/selftests/test-drm_modeset_common.c delete mode 100644 drivers/gpu/drm/selftests/test-drm_modeset_common.h delete mode 100644 drivers/gpu/drm/selftests/test-drm_plane_helper.c delete mode 100644 drivers/gpu/drm/selftests/test-drm_rect.c create mode 100644 drivers/gpu/drm/test/Makefile create mode 100644 drivers/gpu/drm/test/test-drm_cmdline_parser.c create mode 100644 drivers/gpu/drm/test/test-drm_damage_helper.c create mode 100644 drivers/gpu/drm/test/test-drm_dp_mst_helper.c create mode 100644 drivers/gpu/drm/test/test-drm_format.c rename drivers/gpu/drm/{selftests => test}/test-drm_framebuffer.c (91%) create mode 100644 drivers/gpu/drm/test/test-drm_mm.c create mode 100644 drivers/gpu/drm/test/test-drm_plane_helper.c create mode 100644 drivers/gpu/drm/test/test-drm_rect.c -- 2.34.1

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Re: Phyr Starter
by John Hubbard 20 Jan '22

20 Jan '22

On 1/20/22 6:12 AM, Christoph Hellwig wrote: > On Tue, Jan 11, 2022 at 12:17:18AM -0800, John Hubbard wrote: >> Zooming in on the pinning aspect for a moment: last time I attempted to >> convert O_DIRECT callers from gup to pup, I recall wanting very much to >> record, in each bio_vec, whether these pages were acquired via FOLL_PIN, >> or some non-FOLL_PIN method. Because at the end of the IO, it is not >> easy to disentangle which pages require put_page() and which require >> unpin_user_page*(). > > I don't think that is a problem. Pinning only need to happen for > ITER_IOVEC, and the only non-user pages there is the ZERO_PAGE added > for padding that can be special cased. I am really glad to hear you say that. Because I just worked through it again in detail yesterday (including your and others' old emails about this), and tentatively reached the same conclusion from seeing the call paths. But I wanted to confirm with someone who actually knows this code well, and that's not me. :) Things like dio_refill_pages() are mixing in the zero page, but like you say, that can be handled. I have a few ideas for that. Now that the goal is a considerably narrower as compared to in 2019 ("convert DIO callers to pup", instead of "convert the world to pup", ha), this looks quite feasible after all. thanks, -- John Hubbard NVIDIA

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[CI] drm/i915/wopcm: Handle pre-programmed WOPCM registers
by Daniele Ceraolo Spurio 20 Jan '22

20 Jan '22

Starting from DG2, some of the programming previously done by i915 and the GuC has been moved to the GSC and the relevant registers are no longer writable by either CPU or GuC. This is also referred to as GuC deprivilege. On the i915 side, this affects the WOPCM registers: these are no longer programmed by the driver and we do instead expect to find them already set. This can lead to verification failures because in i915 we cheat a bit with the WOPCM size defines, to keep the code common across platforms, by sometimes using a smaller WOPCM size that the actual HW support (which isn't a problem because the extra size is not needed if the FW fits in the smaller chunk), while the pre-programmed values can use the actual size. Given tha the new programming entity is trusted, relax the amount of the checks done on the pre-programmed values by not limiting the max programmed size. In the extremely unlikely scenario that the registers have been misprogrammed, we will still fail later at DMA time. v2: drop special case for DG2 G10 A0 (Alan) Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio(a)intel.com> Cc: Stuart Summers <stuart.summers(a)intel.com> Cc: John Harrison <john.c.harrison(a)intel.com> Cc: Alan Previn <alan.previn.teres.alexis(a)intel.com> Reviewed-by Alan Previn <alan.previn.teres.alexis(a)intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 3 ++ drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_wopcm.c | 42 ++++++++++++++++++---- 5 files changed, 43 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h index e6bd66d6ce5a..cdb47c2291c8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h @@ -94,6 +94,9 @@ #define GUC_ENABLE_MIA_CLOCK_GATING (1<<15) #define GUC_GEN10_SHIM_WC_ENABLE (1<<21) +#define GUC_SHIM_CONTROL2 _MMIO(0xc068) +#define GUC_IS_PRIVILEGED (1<<29) + #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) #define GUC_SEND_TRIGGER (1<<0) #define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 890f1f6fbc49..0ba820ec4e49 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1557,6 +1557,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define INTEL_DISPLAY_ENABLED(dev_priv) \ (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) +#define HAS_GUC_DEPRIVILEGE(dev_priv) \ + (INTEL_INFO(dev_priv)->has_guc_deprivilege) + static inline bool run_as_guest(void) { return !hypervisor_is_type(X86_HYPER_NATIVE); diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 8261b6455747..983546d5f415 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1045,6 +1045,7 @@ static const struct intel_device_info dg2_info = { .graphics.rel = 55, .media.rel = 55, PLATFORM(INTEL_DG2), + .has_guc_deprivilege = 1, .has_64k_pages = 1, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 3699b1c539ea..abf1e103c558 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -134,6 +134,7 @@ enum intel_ppgtt_type { func(has_reset_engine); \ func(has_global_mocs); \ func(has_gt_uc); \ + func(has_guc_deprivilege); \ func(has_l3_dpf); \ func(has_llc); \ func(has_logical_ring_contexts); \ diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index f06d21005106..322fb9eeb880 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -43,6 +43,7 @@ /* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */ #define GEN11_WOPCM_SIZE SZ_2M #define GEN9_WOPCM_SIZE SZ_1M +#define MAX_WOPCM_SIZE SZ_8M /* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */ #define WOPCM_RESERVED_SIZE SZ_16K @@ -207,6 +208,14 @@ static bool __wopcm_regs_locked(struct intel_uncore *uncore, return true; } +static bool __wopcm_regs_writable(struct intel_uncore *uncore) +{ + if (!HAS_GUC_DEPRIVILEGE(uncore->i915)) + return true; + + return intel_uncore_read(uncore, GUC_SHIM_CONTROL2) & GUC_IS_PRIVILEGED; +} + /** * intel_wopcm_init() - Initialize the WOPCM structure. * @wopcm: pointer to intel_wopcm. @@ -224,18 +233,19 @@ void intel_wopcm_init(struct intel_wopcm *wopcm) u32 guc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.guc.fw); u32 huc_fw_size = intel_uc_fw_get_upload_size(&gt->uc.huc.fw); u32 ctx_rsvd = context_reserved_size(i915); + u32 wopcm_size = wopcm->size; u32 guc_wopcm_base; u32 guc_wopcm_size; if (!guc_fw_size) return; - GEM_BUG_ON(!wopcm->size); + GEM_BUG_ON(!wopcm_size); GEM_BUG_ON(wopcm->guc.base); GEM_BUG_ON(wopcm->guc.size); - GEM_BUG_ON(guc_fw_size >= wopcm->size); - GEM_BUG_ON(huc_fw_size >= wopcm->size); - GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm->size); + GEM_BUG_ON(guc_fw_size >= wopcm_size); + GEM_BUG_ON(huc_fw_size >= wopcm_size); + GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm_size); if (i915_inject_probe_failure(i915)) return; @@ -243,6 +253,24 @@ void intel_wopcm_init(struct intel_wopcm *wopcm) if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) { drm_dbg(&i915->drm, "GuC WOPCM is already locked [%uK, %uK)\n", guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K); + /* + * Note that to keep things simple (i.e. avoid different + * defines per platform) our WOPCM math doesn't always use the + * actual WOPCM size, but a value that is less or equal to it. + * This is perfectly fine when i915 programs the registers, but + * on platforms with GuC deprivilege the registers are not + * writable from i915 and are instead pre-programmed by the + * bios/IFWI, so there might be a mismatch of sizes. + * Instead of handling the size difference, we trust that the + * programmed values make sense and disable the relevant check + * by using the maximum possible WOPCM size in the verification + * math. In the extremely unlikely case that the registers + * were pre-programmed with an invalid value, we will still + * gracefully fail later during the GuC/HuC dma. + */ + if (!__wopcm_regs_writable(gt->uncore)) + wopcm_size = MAX_WOPCM_SIZE; + goto check; } @@ -257,17 +285,17 @@ void intel_wopcm_init(struct intel_wopcm *wopcm) * Need to clamp guc_wopcm_base now to make sure the following math is * correct. Formal check of whole WOPCM layout will be done below. */ - guc_wopcm_base = min(guc_wopcm_base, wopcm->size - ctx_rsvd); + guc_wopcm_base = min(guc_wopcm_base, wopcm_size - ctx_rsvd); /* Aligned remainings of usable WOPCM space can be assigned to GuC. */ - guc_wopcm_size = wopcm->size - ctx_rsvd - guc_wopcm_base; + guc_wopcm_size = wopcm_size - ctx_rsvd - guc_wopcm_base; guc_wopcm_size &= GUC_WOPCM_SIZE_MASK; drm_dbg(&i915->drm, "Calculated GuC WOPCM [%uK, %uK)\n", guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K); check: - if (__check_layout(i915, wopcm->size, guc_wopcm_base, guc_wopcm_size, + if (__check_layout(i915, wopcm_size, guc_wopcm_base, guc_wopcm_size, guc_fw_size, huc_fw_size)) { wopcm->guc.base = guc_wopcm_base; wopcm->guc.size = guc_wopcm_size; -- 2.25.1

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[PATCH] drm/i915: Lock timeline mutex directly in error path of eb_pin_timeline
by Matthew Brost 20 Jan '22

20 Jan '22

Don't use the interruptable version of the timeline mutex lock in the error path of eb_pin_timeline as the cleanup must always happen. v2: (John Harrison) - Don't check for interrupt during mutex lock v3: (Tvrtko) - A comment explaining why lock helper isn't used Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf") Signed-off-by: Matthew Brost <matthew.brost(a)intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 9e221ce427075..4a611d62e991a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -2518,9 +2518,14 @@ static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce, timeout) < 0) { i915_request_put(rq); - tl = intel_context_timeline_lock(ce); + /* + * Error path, cannot use intel_context_timeline_lock as + * that is user interruptable and this clean up step + * must be done. + */ + mutex_lock(&ce->timeline->mutex); intel_context_exit(ce); - intel_context_timeline_unlock(tl); + mutex_unlock(&ce->timeline->mutex); if (nonblock) return -EWOULDBLOCK; -- 2.34.1

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[PATCH v3 0/5] discrete card 64K page support
by Robert Beckett 20 Jan '22

20 Jan '22

This series continues support for 64K pages for discrete cards. It supersedes the 64K patches from https://patchwork.freedesktop.org/series/95686/#rev4 Changes since that series: - set min alignment for DG2 to 2MB in i915_address_space_init - replace coloring with simpler 2MB VA alignment for lmem buffers - enforce alignment to 2MB for lmem objects on DG2 in i915_vma_insert - expand vma reservation to round up to 2MB on DG2 in i915_vma_insert - add alignment test v2: rebase and fix for async vma that landed v3: * fix uapi doc typos * add needs_compact_pt flag patch * cleanup vma expansion to use vm->min_alignment instead of hard coding Matthew Auld (3): drm/i915: enforce min GTT alignment for discrete cards drm/i915: support 64K GTT pages for discrete cards drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C (1): drm/i915: add needs_compact_pt flag Robert Beckett (1): drm/i915: add gtt misalignment test .../gpu/drm/i915/gem/selftests/huge_pages.c | 60 +++++ .../i915/gem/selftests/i915_gem_client_blt.c | 23 +- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 108 ++++++++- drivers/gpu/drm/i915/gt/intel_gtt.c | 12 + drivers/gpu/drm/i915/gt/intel_gtt.h | 18 ++ drivers/gpu/drm/i915/gt/intel_ppgtt.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 10 +- drivers/gpu/drm/i915/i915_pci.c | 2 + drivers/gpu/drm/i915/i915_vma.c | 9 + drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 226 +++++++++++++++--- include/uapi/drm/i915_drm.h | 44 +++- 12 files changed, 462 insertions(+), 52 deletions(-) -- 2.25.1

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[PATCH 1/2] dt-bindings: display: bridge: drop Enric Balletbo i Serra from maintainers
by Krzysztof Kozlowski 20 Jan '22

20 Jan '22

Enric Balletbo i Serra emails bounce: <enric.balletbo(a)collabora.com>: Recipient address rejected: User unknown in local recipient table so drop him from the maintainers, similarly to commit 3119c28634dd ("MAINTAINERS: Chrome: Drop Enric Balletbo i Serra"). Add generic DRM bridge maintainers to Analogix ANX7814. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)canonical.com> --- .../devicetree/bindings/display/bridge/analogix,anx7814.yaml | 4 +++- .../bindings/display/bridge/google,cros-ec-anx7688.yaml | 1 - Documentation/devicetree/bindings/display/bridge/ps8640.yaml | 1 - 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml index 8e13f27b28ed..bce96b5b0db0 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7814.yaml @@ -7,7 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analogix ANX7814 SlimPort (Full-HD Transmitter) maintainers: - - Enric Balletbo i Serra <enric.balletbo(a)collabora.com> + - Andrzej Hajda <andrzej.hajda(a)intel.com> + - Neil Armstrong <narmstrong(a)baylibre.com> + - Robert Foss <robert.foss(a)linaro.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml b/Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml index 9f7cc6b757cb..a88a5d8c7ba5 100644 --- a/Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml +++ b/Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml @@ -8,7 +8,6 @@ title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port maintainers: - Nicolas Boichat <drinkcat(a)chromium.org> - - Enric Balletbo i Serra <enric.balletbo(a)collabora.com> description: | ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to diff --git a/Documentation/devicetree/bindings/display/bridge/ps8640.yaml b/Documentation/devicetree/bindings/display/bridge/ps8640.yaml index cdaf7a7a8f88..186e17be51fb 100644 --- a/Documentation/devicetree/bindings/display/bridge/ps8640.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ps8640.yaml @@ -8,7 +8,6 @@ title: MIPI DSI to eDP Video Format Converter Device Tree Bindings maintainers: - Nicolas Boichat <drinkcat(a)chromium.org> - - Enric Balletbo i Serra <enric.balletbo(a)collabora.com> description: | The PS8640 is a low power MIPI-to-eDP video format converter supporting -- 2.32.0

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[PATCH] drm: Add PSR version 4 macro
by sunpeng.li＠amd.com 20 Jan '22

20 Jan '22

From: Leo Li <sunpeng.li(a)amd.com> eDP 1.5 specification defines PSR version 4. It defines PSR1 and PSR2 support with selective-update (SU) capabilities, with additional support for Y-coordinate and Early Transport of the selective-update region. This differs from PSR version 3 in that early transport is supported for version 4, but not for version 3. Signed-off-by: Leo Li <sunpeng.li(a)amd.com> --- include/drm/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 3f2715eb965f..05268c51acaa 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -360,6 +360,7 @@ struct drm_dp_aux; # define DP_PSR_IS_SUPPORTED 1 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ +# define DP_PSR2_WITH_ET_IS_SUPPORTED 4 /* eDP 1.5 (eDP 1.4b SCR) */ #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ # define DP_PSR_NO_TRAIN_ON_EXIT 1 -- 2.34.1

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dri-devel January 2022