dri-devel June 2022

dri-devel@lists.freedesktop.org

332 participants
697 discussions

[PATCH 1/2] iommu: arm-smmu-impl: Add 8250 display compatible to the client list.
by Emma Anholt 18 Jun '22

18 Jun '22

Required for turning on per-process page tables for the GPU. Signed-off-by: Emma Anholt <emma(a)anholt.net> --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index d8e1ef83c01b..bb9220937068 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -233,6 +233,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,sc7280-mdss" }, { .compatible = "qcom,sc7280-mss-pil" }, { .compatible = "qcom,sc8180x-mdss" }, + { .compatible = "qcom,sm8250-mdss" }, { .compatible = "qcom,sdm845-mdss" }, { .compatible = "qcom,sdm845-mss-pil" }, { } -- 2.36.1

3 4

[PATCH] drm: panel-orientation-quirks: Add quirk for Aya Neo Next
by Maccraft123 18 Jun '22

18 Jun '22

From: Maya Matuszczyk <maccraft123mc(a)gmail.com> The device is identified by "NEXT" in board name, however there are different versions of it, "Next Advance" and "Next Pro", that have different DMI board names. Due to a production error a batch or two have their board names prefixed by "AYANEO" and that's how we ended up with 6 different entries for what's basically one device with different hardware specifications. Signed-off-by: Maya Matuszczyk <maccraft123mc(a)gmail.com> --- .../gpu/drm/drm_panel_orientation_quirks.c | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index 4e853acfd1e8..62fc7eb69341 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -152,6 +152,42 @@ static const struct dmi_system_id orientation_data[] = { DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "AYA NEO 2021"), }, .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* AYA NEO NEXT */ + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "NEXT"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* AYA NEO NEXT Advance */ + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "NEXT Advance"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* AYA NEO NEXT Pro */ + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "NEXT Pro"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* AYA NEO NEXT (Batch with different board name) */ + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "AYANEO NEXT"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* AYA NEO NEXT Advance (Batch with different board name) */ + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "AYANEO NEXT Advance"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* AYA NEO NEXT Pro (Batch with different board name) */ + .matches = { + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AYANEO"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "AYANEO NEXT Pro"), + }, + .driver_data = (void *)&lcd800x1280_rightside_up, }, { /* Chuwi HiBook (CWI514) */ .matches = { DMI_MATCH(DMI_BOARD_VENDOR, "Hampoo"), -- 2.36.1

3 3

[PATCH] drm/ssd130x: Use new regmap bulk write support to drop custom bus
by Javier Martinez Canillas 18 Jun '22

18 Jun '22

Data writes for the ssd130x 4-wire SPI protocol need special handling, due the Data/Command control (D/C) pin having to be toggled prior to the write. The regmap API only allowed drivers to provide .reg_{read,write} callbacks to do per register read/write, but didn't provide a way for drivers to do the same for bulk read/writes. For this reason, a custom regmap bus was used by the driver just to define a bulk write callback that implements the D/C pin toggling. But the regmap API has been extended to support defining bulk read/write handlers, so the custom regmap bus is not needed anymore and could just be dropped. Signed-off-by: Javier Martinez Canillas <javierm(a)redhat.com> --- This patch depends on the following regmap fixes: https://lkml.org/lkml/2022/6/16/198 drivers/gpu/drm/solomon/ssd130x-spi.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/solomon/ssd130x-spi.c b/drivers/gpu/drm/solomon/ssd130x-spi.c index 43722adab1f8..72f066ccd2d9 100644 --- a/drivers/gpu/drm/solomon/ssd130x-spi.c +++ b/drivers/gpu/drm/solomon/ssd130x-spi.c @@ -18,11 +18,6 @@ struct ssd130x_spi_transport { struct gpio_desc *dc; }; -static const struct regmap_config ssd130x_spi_regmap_config = { - .reg_bits = 8, - .val_bits = 8, -}; - /* * The regmap bus .write handler, it is just a wrapper around spi_write() * but toggling the Data/Command control pin (D/C#). Since for 4-wire SPI @@ -56,17 +51,12 @@ static int ssd130x_spi_read(void *context, const void *reg, size_t reg_size, return -EOPNOTSUPP; } -/* - * A custom bus is needed due the special write that toggles a D/C# pin, - * another option could be to just have a .reg_write() callback but that - * will prevent to do data writes in bulk. - * - * Once the regmap API is extended to support defining a bulk write handler - * in the struct regmap_config, this can be simplified and the bus dropped. - */ -static struct regmap_bus regmap_ssd130x_spi_bus = { +static const struct regmap_config ssd130x_spi_regmap_config = { + .reg_bits = 8, + .val_bits = 8, .write = ssd130x_spi_write, .read = ssd130x_spi_read, + .can_multi_write = true, }; static int ssd130x_spi_probe(struct spi_device *spi) @@ -90,8 +80,7 @@ static int ssd130x_spi_probe(struct spi_device *spi) t->spi = spi; t->dc = dc; - regmap = devm_regmap_init(dev, &regmap_ssd130x_spi_bus, t, - &ssd130x_spi_regmap_config); + regmap = devm_regmap_init(dev, NULL, t, &ssd130x_spi_regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); -- 2.36.1

1 0

[PATCH] drm/rockchip: Fix an error handling path rockchip_dp_probe()
by Christophe JAILLET 18 Jun '22

18 Jun '22

Should component_add() fail, we should call analogix_dp_remove() in the error handling path, as already done in the remove function. Fixes: 152cce0006ab ("drm/bridge: analogix_dp: Split bind() into probe() and real bind()") Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 70be64ca0a00..ad2d3ae7e621 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -408,7 +408,15 @@ static int rockchip_dp_probe(struct platform_device *pdev) if (IS_ERR(dp->adp)) return PTR_ERR(dp->adp); - return component_add(dev, &rockchip_dp_component_ops); + ret = component_add(dev, &rockchip_dp_component_ops); + if (ret) + goto err_dp_remove; + + return 0; + +err_dp_remove: + analogix_dp_remove(dp->adp); + return ret; } static int rockchip_dp_remove(struct platform_device *pdev) -- 2.34.1

1 0

[PATCH v2 1/2] drm/msm: Drop update_fences()
by Rob Clark 18 Jun '22

18 Jun '22

From: Rob Clark <robdclark(a)chromium.org> I noticed while looking at some traces, that we could miss calls to msm_update_fence(), as the irq could have raced with retire_submits() which could have already popped the last submit on a ring out of the queue of in-flight submits. But walking the list of submits in the irq handler isn't really needed, as dma_fence_is_signaled() will dtrt. So lets just drop it entirely. v2: use spin_lock_irqsave/restore as we are no longer protected by the spin_lock_irqsave/restore() in update_fences() Reported-by: Steev Klimaszewski <steev(a)kali.org> Fixes: 95d1deb02a9c ("drm/msm/gem: Add fenced vma unpin") Signed-off-by: Rob Clark <robdclark(a)chromium.org> Tested-by: Steev Klimaszewski <steev(a)kali.org> --- drivers/gpu/drm/msm/msm_fence.c | 8 +++++--- drivers/gpu/drm/msm/msm_gpu.c | 22 ++-------------------- 2 files changed, 7 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c index 3df255402a33..38e3323bc232 100644 --- a/drivers/gpu/drm/msm/msm_fence.c +++ b/drivers/gpu/drm/msm/msm_fence.c @@ -46,12 +46,14 @@ bool msm_fence_completed(struct msm_fence_context *fctx, uint32_t fence) (int32_t)(*fctx->fenceptr - fence) >= 0; } -/* called from workqueue */ +/* called from irq handler and workqueue (in recover path) */ void msm_update_fence(struct msm_fence_context *fctx, uint32_t fence) { - spin_lock(&fctx->spinlock); + unsigned long flags; + + spin_lock_irqsave(&fctx->spinlock, flags); fctx->completed_fence = max(fence, fctx->completed_fence); - spin_unlock(&fctx->spinlock); + spin_unlock_irqrestore(&fctx->spinlock, flags); } struct msm_fence { diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 244511f85044..cedc88cf8083 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -164,24 +164,6 @@ int msm_gpu_hw_init(struct msm_gpu *gpu) return ret; } -static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring, - uint32_t fence) -{ - struct msm_gem_submit *submit; - unsigned long flags; - - spin_lock_irqsave(&ring->submit_lock, flags); - list_for_each_entry(submit, &ring->submits, node) { - if (fence_after(submit->seqno, fence)) - break; - - msm_update_fence(submit->ring->fctx, - submit->hw_fence->seqno); - dma_fence_signal(submit->hw_fence); - } - spin_unlock_irqrestore(&ring->submit_lock, flags); -} - #ifdef CONFIG_DEV_COREDUMP static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, size_t count, void *data, size_t datalen) @@ -438,7 +420,7 @@ static void recover_worker(struct kthread_work *work) if (ring == cur_ring) fence++; - update_fences(gpu, ring, fence); + msm_update_fence(ring->fctx, fence); } if (msm_gpu_active(gpu)) { @@ -736,7 +718,7 @@ void msm_gpu_retire(struct msm_gpu *gpu) int i; for (i = 0; i < gpu->nr_rings; i++) - update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence); + msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence); kthread_queue_work(gpu->worker, &gpu->retire_work); update_sw_cntrs(gpu); -- 2.36.1

1 1

[PATCH 1/5] drm/msm: less magic numbers in msm_mdss_enable
by Dmitry Baryshkov 18 Jun '22

18 Jun '22

Replace magic register writes in msm_mdss_enable() with version that contains less magic and more variable names that can be traced back to the dpu_hw_catalog or the downstream dtsi files. Reviewed-by: Abhinav Kumar <quic_abhinavk(a)quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov(a)linaro.org> --- drivers/gpu/drm/msm/msm_mdss.c | 80 ++++++++++++++++++++++++++++++---- 1 file changed, 72 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 0454a571adf7..b41848bfff91 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -21,6 +21,7 @@ #define HW_REV 0x0 #define HW_INTR_STATUS 0x0010 +#define UBWC_DEC_HW_VERSION 0x58 #define UBWC_STATIC 0x144 #define UBWC_CTRL_2 0x150 #define UBWC_PREDICTION_MODE 0x154 @@ -132,9 +133,63 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) return 0; } +#define UBWC_1_0 0x10000000 +#define UBWC_2_0 0x20000000 +#define UBWC_3_0 0x30000000 +#define UBWC_4_0 0x40000000 + +static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss, + u32 ubwc_static) +{ + writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC); +} + +static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss, + unsigned int ubwc_version, + u32 ubwc_swizzle, + u32 highest_bank_bit, + u32 macrotile_mode) +{ + u32 value = (ubwc_swizzle & 0x1) | + (highest_bank_bit & 0x3) << 4 | + (macrotile_mode & 0x1) << 12; + + if (ubwc_version == UBWC_3_0) + value |= BIT(10); + + if (ubwc_version == UBWC_1_0) + value |= BIT(8); + + writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); +} + +static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss, + unsigned int ubwc_version, + u32 ubwc_swizzle, + u32 ubwc_static, + u32 highest_bank_bit, + u32 macrotile_mode) +{ + u32 value = (ubwc_swizzle & 0x7) | + (ubwc_static & 0x1) << 3 | + (highest_bank_bit & 0x7) << 4 | + (macrotile_mode & 0x1) << 12; + + writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); + + if (ubwc_version == UBWC_3_0) { + writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); + writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); + } else { + writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); + } +} + static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret; + u32 hw_rev; ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); if (ret) { @@ -149,26 +204,35 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) if (msm_mdss->is_mdp5) return 0; + hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV); + dev_dbg(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev); + dev_dbg(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", + readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); + /* * ubwc config is part of the "mdss" region which is not accessible * from the rest of the driver. hardcode known configurations here + * + * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, + * UBWC_n and the rest of params comes from hw_catalog. + * Unforunately this driver can not access hw catalog, so we have to + * hardcode them here. */ - switch (readl_relaxed(msm_mdss->mmio + HW_REV)) { + switch (hw_rev) { case DPU_HW_VER_500: case DPU_HW_VER_501: - writel_relaxed(0x420, msm_mdss->mmio + UBWC_STATIC); + msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0); break; case DPU_HW_VER_600: - /* TODO: 0x102e for LP_DDR4 */ - writel_relaxed(0x103e, msm_mdss->mmio + UBWC_STATIC); - writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); - writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1); break; case DPU_HW_VER_620: - writel_relaxed(0x1e, msm_mdss->mmio + UBWC_STATIC); + /* UBWC_2_0 */ + msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e); break; case DPU_HW_VER_720: - writel_relaxed(0x101e, msm_mdss->mmio + UBWC_STATIC); + msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1); break; } -- 2.35.1

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[PATCH] drm/bochs: Fix some error handling paths in bochs_pci_probe()
by Christophe JAILLET 18 Jun '22

18 Jun '22

The remove() function calls bochs_hw_fini() but this function is not called in the error handling of the probe. This call releases the resources allocated by bochs_hw_init() used in bochs_load(). Update the probe and bochs_load() to call bochs_hw_fini() if an error occurs after a successful bochs_hw_init() call. Signed-off-by: Christophe JAILLET <christophe.jaillet(a)wanadoo.fr> --- I've not been able to find a Fixes: tag because of code re-arrangement done in 796c3e35ac16. --- drivers/gpu/drm/tiny/bochs.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tiny/bochs.c b/drivers/gpu/drm/tiny/bochs.c index 4f8bf86633df..d7a34ed4be3e 100644 --- a/drivers/gpu/drm/tiny/bochs.c +++ b/drivers/gpu/drm/tiny/bochs.c @@ -581,13 +581,17 @@ static int bochs_load(struct drm_device *dev) ret = drmm_vram_helper_init(dev, bochs->fb_base, bochs->fb_size); if (ret) - return ret; + goto err_hw_fini; ret = bochs_kms_init(bochs); if (ret) - return ret; + goto err_hw_fini; return 0; + +err_hw_fini: + bochs_hw_fini(dev); + return ret; } DEFINE_DRM_GEM_FOPS(bochs_fops); @@ -662,11 +666,13 @@ static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent ret = drm_dev_register(dev, 0); if (ret) - goto err_free_dev; + goto err_hw_fini; drm_fbdev_generic_setup(dev, 32); return ret; +err_hw_fini: + bochs_hw_fini(dev); err_free_dev: drm_dev_put(dev); return ret; -- 2.34.1

1 0

[PATCH] video: fbdev: Fix refcount leak bug in valkyriefb.c
by Liang He 18 Jun '22

18 Jun '22

In valkyriefb_init(), of_find_node_by_name() will return a node pointer with refcount incremented. We should use of_node_put() in fail path or when it is not used anymore. Signed-off-by: Liang He <windhl(a)126.com> --- drivers/video/fbdev/valkyriefb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/fbdev/valkyriefb.c b/drivers/video/fbdev/valkyriefb.c index a6c9d4f26669..20d727a8069d 100644 --- a/drivers/video/fbdev/valkyriefb.c +++ b/drivers/video/fbdev/valkyriefb.c @@ -334,10 +334,13 @@ int __init valkyriefb_init(void) return 0; if (of_address_to_resource(dp, 0, &r)) { + of_node_put(dp); printk(KERN_ERR "can't find address for valkyrie\n"); return 0; } + of_node_put(dp); + frame_buffer_phys = r.start; cmap_regs_phys = r.start + 0x304000; } -- 2.25.1

1 0

[PATCH v6 0/4] drm/msm: convet to drm_crtc_handle_vblank()
by Dmitry Baryshkov 17 Jun '22

17 Jun '22

This patchseries replaces drm_handle_vblank() with drm_crtc_handle_vblank(). As a bonus result of this conversion it is possible to drop the stored array of allocated CRTCs and use the core CRTC iterators. Changes since v5: - Clean up the event_thread->worker in case of an error to fix possible oops in msm_drm_uninit(). Changes since v4: - Removed the duplicate word 'duplicate' from the last patch'es commit message (noticed by Abhinav). Changes since v3: - In msm_drm_init simplify the code by using an interim var for the event thread itself rather than just the index (suggested by Abhinav) Changes since v2; - none (sent by mistake) Changes since v1; - fixed uninitialized var access (LTP Robot) Dmitry Baryshkov (4): drm/msm: clean event_thread->worker in case of an error drm/msm/mdp4: convert to drm_crtc_handle_vblank() drm/msm/mdp5: convert to drm_crtc_handle_vblank() drm/msm: stop storing the array of CRTCs in struct msm_drm_private drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c | 9 +++-- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c | 9 +++-- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 +- drivers/gpu/drm/msm/msm_drv.c | 44 +++++++++++++----------- drivers/gpu/drm/msm/msm_drv.h | 3 +- 7 files changed, 35 insertions(+), 36 deletions(-) -- 2.35.1

1 4

[PATCH] dt-bindings: display: delete ilitek,ili9341.txt
by Conor Dooley 17 Jun '22

17 Jun '22

From: Conor Dooley <conor.dooley(a)microchip.com> ilitek,ili9341.txt was replaced by ilitek,ili9341.yaml but the txt binding was not deleted. Do so. Signed-off-by: Conor Dooley <conor.dooley(a)microchip.com> --- .../bindings/display/ilitek,ili9341.txt | 27 ------------------- 1 file changed, 27 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt deleted file mode 100644 index 169b32e4ee4e..000000000000 --- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt +++ /dev/null @@ -1,27 +0,0 @@ -Ilitek ILI9341 display panels - -This binding is for display panels using an Ilitek ILI9341 controller in SPI -mode. - -Required properties: -- compatible: "adafruit,yx240qv29", "ilitek,ili9341" -- dc-gpios: D/C pin -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) -- backlight: phandle of the backlight device attached to the panel - -Example: - display@0{ - compatible = "adafruit,yx240qv29", "ilitek,ili9341"; - reg = <0>; - spi-max-frequency = <32000000>; - dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - rotation = <270>; - backlight = <&backlight>; - }; -- 2.36.1

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dri-devel June 2022