dri-devel June 2022

dri-devel@lists.freedesktop.org

332 participants
697 discussions

[PATCH v2 0/2] drm/vkms: check plane_composer->map[0] before using it
by Tales Lelo da Aparecida 13 Jun '22

13 Jun '22

Hi, this is a follow-up of my last patch. Thanks for the reviews! Changes from v1: Edit the first commit message as suggested by Melissa and add a commit to enhance the error handling (André) Tales Lelo da Aparecida (2): drm/vkms: check plane_composer->map[0] before using it drm/vkms: return early if compose_plane fails drivers/gpu/drm/vkms/vkms_composer.c | 32 ++++++++++++++++++---------- 1 file changed, 21 insertions(+), 11 deletions(-) -- 2.35.1

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[PATCH 1/5] drm/arm: Fix spelling typo in comments
by 1064094935＠qq.com 13 Jun '22

13 Jun '22

From: pengfuyuan <pengfuyuan(a)kylinos.cn> Fix spelling typo in comments. Reported-by: k2ci <kernel-bot(a)kylinos.cn> Signed-off-by: pengfuyuan <pengfuyuan(a)kylinos.cn> --- drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 2 +- drivers/gpu/drm/arm/malidp_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c index e672b9cffee3..3276a3e82c62 100644 --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c @@ -1271,7 +1271,7 @@ int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe, return 0; } -/* Since standalong disabled components must be disabled separately and in the +/* Since standalone disabled components must be disabled separately and in the * last, So a complete disable operation may needs to call pipeline_disable * twice (two phase disabling). * Phase 1: disable the common components, flush it. diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 514c50dcb74d..59f63cc2b304 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -145,7 +145,7 @@ #define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff #define MALIDP_SE_SET_COEFFTAB_DATA(x) \ ((x) & MALIDP_SE_COEFFTAB_DATA_MASK) -/* Enhance coeffents reigster offset */ +/* Enhance coeffents register offset */ #define MALIDP_SE_IMAGE_ENH 0x3C /* ENH_LIMITS offset 0x0 */ #define MALIDP_SE_ENH_LOW_LEVEL 24 -- 2.25.1 No virus found Checked by Hillstone Network AntiVirus

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[PATCH 0/2] i915: Extract, polish, and document multicast handling
by Matt Roper 13 Jun '22

13 Jun '22

Multicast/replicated (MCR) registers on Intel hardware are a purely GT-specific concept. Rather than leaving MCR register handling spread across several places throughout the driver (intel_uncore.c, intel_gt.c, etc.) with confusing combinations of handler functions living in different namespaces, let's consolidate it all into a single place (intel_gt_mcr.c) and provide a more consistent and clearly-documented interface for the rest of the driver to access such registers: * intel_gt_mcr_read -- unicast read from specific instance * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated instance * intel_gt_mcr_unicast_write -- unicast write to specific instance * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances Matt Roper (2): drm/i915/gt: Move multicast register handling to a dedicated file drm/i915/gt: Cleanup interface for MCR operations drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 36 +- drivers/gpu/drm/i915/gt/intel_gt.c | 297 +----------- drivers/gpu/drm/i915/gt/intel_gt.h | 15 - drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 483 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 34 ++ drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/intel_uncore.c | 112 ----- drivers/gpu/drm/i915/intel_uncore.h | 8 - 14 files changed, 551 insertions(+), 460 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h -- 2.35.3

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[PATCH 0/1] For stable: "drm/ast: Create threshold values for AST2600"
by Thomas Zimmermann 13 Jun '22

13 Jun '22

Mainline commit bcc77411e8a6 ("drm/ast: Create threshold values for AST2600") needs backporting into older Linux kernels. The earliest affected version is v5.11. KuoHsiang Chou (1): drm/ast: Create threshold values for AST2600 drivers/gpu/drm/ast/ast_mode.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.36.1

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[Bug 213145] New: AMDGPU resets, timesout and crashes after "*ERROR* Waiting for fences timed out!"
by bugzilla-daemon＠bugzilla.kernel.org 13 Jun '22

13 Jun '22

https://bugzilla.kernel.org/show_bug.cgi?id=213145 Bug ID: 213145 Summary: AMDGPU resets, timesout and crashes after "*ERROR* Waiting for fences timed out!" Product: Drivers Version: 2.5 Kernel Version: 5.10.37 and 5.10.38 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: high Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri(a)kernel-bugs.osdl.org Reporter: tgayoso(a)gmail.com Regression: No Created attachment 296867 --> https://bugzilla.kernel.org/attachment.cgi?id=296867&action=edit lspci output AMDGPU driver crashes randomly corrupting screen and freezing X with: [ 60.449781] [drm:0xffffffffc25a7a57] *ERROR* Waiting for fences timed out! [ 60.971941] [drm:0xffffffffc25281ae] *ERROR* ring gfx timeout, signaled seq=3658, emitted seq=3660 [ 60.971946] [drm:0xffffffffc25281cb] *ERROR* Process information: process Xorg pid 1192 thread Xorg:cs0 pid 1193 [ 60.971952] amdgpu 0000:05:00.0: amdgpu: GPU reset begin! ... (some output suppressed for clarity, look at attached dmesg, please). [ 61.800343] amdgpu 0000:05:00.0: amdgpu: recover vram bo from shadow start [ 61.800346] amdgpu 0000:05:00.0: amdgpu: recover vram bo from shadow done [ 61.800348] [drm] Skip scheduling IBs! [ 61.800350] [drm] Skip scheduling IBs! [ 61.800382] [drm] Skip scheduling IBs! [ 61.800398] amdgpu 0000:05:00.0: amdgpu: GPU reset(2) succeeded! [ 61.800566] [drm] Skip scheduling IBs! [ 61.800580] [drm] Skip scheduling IBs! [ 61.800627] [drm] Skip scheduling IBs! [ 61.801012] [drm] Skip scheduling IBs! [ 61.801024] [drm] Skip scheduling IBs! [ 61.801052] [drm] Skip scheduling IBs! [ 61.801062] [drm] Skip scheduling IBs! [ 61.801096] [drm] Skip scheduling IBs! [ 61.801105] [drm] Skip scheduling IBs! [ 61.801137] [drm] Skip scheduling IBs! [ 61.801806] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.808746] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.809392] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.809764] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.810389] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.810866] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.812529] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.813359] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.814770] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 61.816488] [drm:0xffffffffc24219b8] *ERROR* Failed to initialize parser -125! [ 62.541982] ucsi_acpi USBC000:00: PPM init failed (-110) [ 67.004898] amdgpu_cs_ioctl: 1467 callbacks suppressed Hardware: ASUS TUF506IU laptop (dual GPU Renoir and Nvidia GeForce GTX 1660 Ti Mobile) Detailed hardware in lspci.txt. Detailed modules in lsmod.txt. Kernle config attached in Kernel_config. -- You may reply to this email to add a comment. You are receiving this mail because: You are watching the assignee of the bug.

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[PATCH v3 1/2] dt-bindings: display: bridge: Add TI DLPC3433 DSI to DMD
by Jagan Teki 13 Jun '22

13 Jun '22

TI DLPC3433 is a MIPI DSI based display controller bridge for processing high resolution DMD based projectors. It has a flexible configuration of MIPI DSI and DPI signal input that produces a DMD output in RGB565, RGB666, RGB888 formats. It supports upto 720p resolution with 60 and 120 Hz refresh rates. Add dt-bingings for it. Signed-off-by: Christopher Vollo <chris(a)renewoutreach.org> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> Reviewed-by: Rob Herring <robh(a)kernel.org> --- Changes for v3: - collect Rob r-b Changes for v2: - fix compatible - drop reg description - fix enable_gpio description - fix port@2 .../bindings/display/bridge/ti,dlpc3433.yaml | 117 ++++++++++++++++++ MAINTAINERS | 5 + 2 files changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml b/Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml new file mode 100644 index 000000000000..542193d77cdf --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DLPC3433 MIPI DSI to DMD bridge + +maintainers: + - Jagan Teki <jagan(a)amarulasolutions.com> + - Christopher Vollo <chris(a)renewoutreach.org> + +description: | + TI DLPC3433 is a MIPI DSI based display controller bridge + for processing high resolution DMD based projectors. + + It has a flexible configuration of MIPI DSI and DPI signal + input that produces a DMD output in RGB565, RGB666, RGB888 + formats. + + It supports upto 720p resolution with 60 and 120 Hz refresh + rates. + +properties: + compatible: + const: ti,dlpc3433 + + reg: + enum: + - 0x1b + - 0x1d + + enable-gpios: + description: PROJ_ON pin, chip powers up PROJ_ON is high. + + vcc_intf-supply: + description: A 1.8V/3.3V supply that power the Host I/O. + + vcc_flsh-supply: + description: A 1.8V/3.3V supply that power the Flash I/O. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Video port for MIPI DSI input. + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for DMD output. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - enable-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@1b { + compatible = "ti,dlpc3433"; + reg = <0x1b>; + enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in_dsi: endpoint { + remote-endpoint = <&dsi_out_bridge>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out_panel: endpoint { + remote-endpoint = <&panel_out_bridge>; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 11da16bfa123..aea0fe5156af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6431,6 +6431,11 @@ DRM DRIVER FOR TDFX VIDEO CARDS S: Orphan / Obsolete F: drivers/gpu/drm/tdfx/ +DRM DRIVER FOR TI DLPC3433 MIPI DSI TO DMD BRIDGE +M: Jagan Teki <jagan(a)amarulasolutions.com> +S: Maintained +F: Documentation/devicetree/bindings/display/bridge/ti,dlpc3433.yaml + DRM DRIVER FOR TI SN65DSI86 BRIDGE CHIP R: Douglas Anderson <dianders(a)chromium.org> F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml -- 2.25.1

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[PATCH -next] drm/syncobj: add missing error return code in drm_syncobj_transfer_to_timeline()
by Yang Yingliang 13 Jun '22

13 Jun '22

If dma_fence_unwrap_merge() fails, it should return error code in drm_syncobj_transfer_to_timeline() Fixes: ec8d985ff26f ("drm: use dma_fence_unwrap_merge() in drm_syncobj") Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Yang Yingliang <yangyingliang(a)huawei.com> --- drivers/gpu/drm/drm_syncobj.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index bbad9e4696e7..0c2be8360525 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -874,8 +874,10 @@ static int drm_syncobj_transfer_to_timeline(struct drm_file *file_private, fence = dma_fence_unwrap_merge(tmp); dma_fence_put(tmp); - if (!fence) + if (!fence) { + ret = -ENOMEM; goto err_put_timeline; + } chain = dma_fence_chain_alloc(); if (!chain) { -- 2.25.1

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[PATCH v10 00/21] drm/mediatek: Add mt8195 DisplayPort driver
by Guillaume Ranquet 13 Jun '22

13 Jun '22

this series is built around the DisplayPort driver. The dpi/dpintf driver and the added helper functions are required for the DisplayPort driver to work. This v10 still has some un-answered comments and TODOs for v11. This has been tested sucessfully on a 5.18-next based "vendor branch". There's a missing dependency in the mediatek clock framework to allow a mux clock to change it's parent automatically on rate change. Without this change, the dpi driver won't properly set the clocks on mode change and thus nothing will be displayed on screen. Changes from v9: - The DP-Phy is back to being a child device of the DP driver (as in v8) - hot plug detection has been added back to Embedded Display Port... as after discussing with mediatek experts, this is needed eventhough the Embedded Display port is not un-pluggable - rebased on linux-next - simplified/split train_handler function, as suggested by Rex - added comments on the sleep/delays present in the code - removed previous patch introducing retries when receiving AUX_DEFER as this is already handled in the dp_aux framework - added max-lane and max-linkrate device tree u8 properties instead of hardcoded #defines Things that are in my todolist for v11: - retrieve CK/DE support from panel driver instead of hardcoding it into the dpi driver - refcount the dp driver "enabled" status for "future proofing" - review the drm_dp_helpers for features/functions that have been re-implemented in the mediatek dp drivers Older revisions: RFC - https://lore.kernel.org/linux-mediatek/20210816192523.1739365-1-msp@baylibr… v1 - https://lore.kernel.org/linux-mediatek/20210906193529.718845-1-msp@baylibre… v2 - https://lore.kernel.org/linux-mediatek/20210920084424.231825-1-msp@baylibre… v3 - https://lore.kernel.org/linux-mediatek/20211001094443.2770169-1-msp@baylibr… v4 - https://lore.kernel.org/linux-mediatek/20211011094624.3416029-1-msp@baylibr… v5 - https://lore.kernel.org/all/20211021092707.3562523-1-msp@baylibre.com/ v6 - https://lore.kernel.org/linux-mediatek/20211110130623.20553-1-granquet@bayl… v7 - https://lore.kernel.org/linux-mediatek/20211217150854.2081-1-granquet@bayli… v8 - https://lore.kernel.org/linux-mediatek/20220218145437.18563-1-granquet@bayl… v9 - https://lore.kernel.org/all/20220327223927.20848-1-granquet@baylibre.com/ Functional dependencies are: - Add Mediatek Soc DRM (vdosys0) support for mt8195 https://lore.kernel.org/linux-mediatek/20220419094143.9561-2-jason-jh.lin@m… - Add MediaTek SoC DRM (vdosys1) support for mt8195 https://lore.kernel.org/linux-mediatek/20220512053128.31415-1-nancy.lin@med… Guillaume Ranquet (15): drm/edid: Convert cea_sad helper struct to kernelDoc drm/edid: Add cea_sad helpers for freq/length drm/mediatek: dpi: move dpi limits to SoC config drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config drm/mediatek: dpi: implement a swap_input toggle in SoC config drm/mediatek: dpi: move dimension mask to SoC config drm/mediatek: dpi: move hvsize_mask to SoC config drm/mediatek: dpi: move swap_shift to SoC config drm/mediatek: dpi: move the yuv422_en_bit to SoC config drm/mediatek: dpi: move the csc_enable bit to SoC config drm/mediatek: dpi: Add dpintf support drm/mediatek: dpi: Only enable dpi after the bridge is enabled drm/meditek: dpi: Add matrix_sel helper drm/mediatek: Add mt8195 External DisplayPort support drm/mediatek: DP audio support for mt8195 Jitao Shi (1): drm/mediatek: add hpd debounce Markus Schneider-Pargmann (5): dt-bindings: mediatek,dpi: Add DPINTF compatible dt-bindings: mediatek,dp: Add Display Port binding video/hdmi: Add audio_infoframe packing for DP phy: phy-mtk-dp: Add driver for DP phy drm/mediatek: Add mt8195 Embedded DisplayPort driver .../display/mediatek/mediatek,dp.yaml | 99 + .../display/mediatek/mediatek,dpi.yaml | 13 +- MAINTAINERS | 1 + drivers/gpu/drm/drm_edid.c | 74 + drivers/gpu/drm/mediatek/Kconfig | 8 + drivers/gpu/drm/mediatek/Makefile | 2 + drivers/gpu/drm/mediatek/mtk_dp.c | 3419 +++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dp_reg.h | 570 +++ drivers/gpu/drm/mediatek/mtk_dpi.c | 272 +- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 38 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 + drivers/phy/mediatek/Kconfig | 8 + drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-dp.c | 200 + drivers/video/hdmi.c | 82 +- include/drm/dp/drm_dp_helper.h | 2 + include/drm/drm_edid.h | 26 +- include/linux/hdmi.h | 7 +- include/linux/soc/mediatek/mtk-mmsys.h | 4 +- 22 files changed, 4765 insertions(+), 81 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h create mode 100644 drivers/phy/mediatek/phy-mtk-dp.c -- 2.35.1

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[LINUX PATCH 0/2] Add Xilinx DSI-Tx DRM driver
by Venkateshwar Rao Gannavarapu 13 Jun '22

13 Jun '22

MIPI DSI TX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between the video processing subsystems and MIPI-based displays. An internal high-speed physical layer design, D-PHY, is provided to allow direct connection to display peripherals. The subsystem consists of the following sub-blocks: - MIPI D-PHY - MIPI DSI TX Controller - AXI Crossbar Please refer pg238 [1]. The DSI TX Controller receives stream of image data through an input stream interface. At design time, this subsystem can be configured to number of lanes and pixel format. This patch series adds the dt-binding and DRM driver for Xilinx DSI-Tx soft IP. References: [1]: https://www.xilinx.com/support/documentation/ip_documentation/mipi_dsi_tx_s… Venkateshwar Rao Gannavarapu (2): dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation drm: xlnx: dsi: driver for Xilinx DSI Tx subsystem .../bindings/display/xlnx/xlnx,dsi-tx.yaml | 105 +++++ drivers/gpu/drm/xlnx/Kconfig | 14 + drivers/gpu/drm/xlnx/Makefile | 1 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 456 +++++++++++++++++++++ 4 files changed, 576 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c -- 1.8.3.1

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[PATCH] drm: rcar-du: Lift z-pos restriction on primary plane for Gen3
by Laurent Pinchart 13 Jun '22

13 Jun '22

There's no reason to require the primary plane to always be at the bottom of the stack, as the VSP supports arbitrary ordering of planes, and the KMS API doesn't have such a requirement either. Lift the restriction. As the primary plane can now be positioned arbitrarily, enable control of its alpha channel as well. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas(a)ideasonboard.com> --- drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c index 6b535abd799a..356861de17b0 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c @@ -431,14 +431,9 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np, drm_plane_helper_add(&plane->plane, &rcar_du_vsp_plane_helper_funcs); - if (type == DRM_PLANE_TYPE_PRIMARY) { - drm_plane_create_zpos_immutable_property(&plane->plane, - 0); - } else { - drm_plane_create_alpha_property(&plane->plane); - drm_plane_create_zpos_property(&plane->plane, 1, 1, - num_planes - 1); - } + drm_plane_create_alpha_property(&plane->plane); + drm_plane_create_zpos_property(&plane->plane, i, 0, + num_planes - 1); vsp->num_planes++; } base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56 -- Regards, Laurent Pinchart

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dri-devel June 2022