drm/amdgpu: apply AMDGPU_IB_FLAG_EMIT_MEM_SYNC to compute IBs too

[Christian König]

Thanks for that explanation. I suspected that there was a good reason to 
have that in the kernel, but couldn't find one.

In this case the patch is Reviewed-by: Christian König 
<christian.koenig at amd.com>

We should probably add this explanation as comment to the flag as well.

Thanks,
Christian.

Am 26.04.20 um 02:43 schrieb Marek Olšák:
> It was merged into amd-staging-drm-next.
>
> I'm not absolutely sure, but I think we need to invalidate before IBs 
> if an IB is cached in L2 and the CPU has updated it. It can only be 
> cached in L2 if something other than CP has read it or written to it 
> without invalidation. CP reads don't cache it but they can hit the 
> cache if it's already cached.
>
> For CE, we need to invalidate before the IB in the kernel, because CE 
> IBs can't do cache invalidations IIRC. This is the number one reason 
> for merging the already pushed commits.
>
> Marek
>
> On Sat., Apr. 25, 2020, 11:03 Christian König, 
> <ckoenig.leichtzumerken at gmail.com 
> <mailto:ckoenig.leichtzumerken at gmail.com>> wrote:
>
>     Was that patch set actually merged upstream? My last status is
>     that we couldn't find a reason why we need to do this in the kernel.
>
>     Christian.
>
>     Am 25.04.20 um 10:52 schrieb Marek Olšák:
>>     This was missed.
>>
>>     Marek
>>
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