[PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

You can probably just squash patches 2-5 into one patch.  Either way, series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: Quan, Evan <Evan.Quan at amd.com>
Sent: Monday, August 17, 2020 3:49 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Quan, Evan <Evan.Quan at amd.com>
Subject: [PATCH 1/5] drm/amd/pm: disable/enable gfx ulv on UMD pstate enter/exit

Add gfx ulv disablement/enablement on UMD pstate entering/exiting.

Change-Id: Ieb38fdb5975b563f24c0b172fedd01acf99afb10
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h     | 1 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c   | 2 ++
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index bbe4a343e9f1..7cc707ec21c3 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -596,6 +596,7 @@ struct pptable_funcs {
         int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
         ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
         int (*enable_mgpu_fan_boost)(struct smu_context *smu);
+       int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
 };

 typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7d17c4f1b489..221b5c923ce1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1440,6 +1440,7 @@ static int smu_enable_umd_pstate(void *handle,
                         amdgpu_device_ip_set_clockgating_state(smu->adev,
                                                                AMD_IP_BLOCK_TYPE_GFX,
                                                                AMD_CG_STATE_UNGATE);
+                       smu_gfx_ulv_control(smu, false);
                 }
         } else {
                 /* exit umd pstate, restore level, enable gfx cg*/
@@ -1447,6 +1448,7 @@ static int smu_enable_umd_pstate(void *handle,
                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
                                 *level = smu_dpm_ctx->saved_dpm_level;
                         smu_dpm_ctx->enable_umd_pstate = false;
+                       smu_gfx_ulv_control(smu, true);
                         amdgpu_device_ip_set_clockgating_state(smu->adev,
                                                                AMD_IP_BLOCK_TYPE_GFX,
                                                                AMD_CG_STATE_GATE);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
index 264073d4e263..2fe29c6a00ce 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h
@@ -92,6 +92,7 @@
 #define smu_get_asic_power_limits(smu)                                  smu_ppt_funcs(get_power_limit, 0, smu)
 #define smu_get_pp_feature_mask(smu, buf)                               smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)
 #define smu_set_pp_feature_mask(smu, new_mask)                          smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
+#define smu_gfx_ulv_control(smu, enablement)                           smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)

 #endif
 #endif
--
2.28.0

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