[Beignet] [PATCH] CL/Driver: enable atomics in L3 for HSW.

[Zhenyu Wang]

On 2014.12.31 03:41:02 +0000, Gong, Zhigang wrote:
> > commit f3fc4884ebe6ae649d3723be14b219230d3b7fd2
> > Author: Francisco Jerez <currojerez at riseup.net>
> > Date:   Wed Oct 2 15:53:16 2013 -0700
> > 
> >     drm/i915/hsw: Disable L3 caching of atomic memory operations.
> > 
> >     Otherwise using any atomic memory operation will lock up the GPU due
> >     to a Haswell hardware bug.
> > 
> > Maybe this issue affects some HSW stepping, should just fix the kernel.
> 
> That should be a hardware bug for the version earlier than stepping D.
> And I think this should not be a real problem now, as all HSW we can get
> from public channel is at least stepping D or newer. I will submit a kernel
> patch latter. Before that patch has been accepted by kernel, I would rather
> to push this patch to beignet. As some application will affected heavily by
> this issue, such as the darktable's splat kernel. The splat kernel uses many
> atomic operations, and may take 50 seconds on one image, but with this patch
> it just takes less than 1 second.
> 
> Any thoughts?
> 

Even if you have this hack in beignet now, you will revert
that anyway in future when upstream cmd parser is ready for Gen7.
As if this load exists in your exec submit, kernel cmd parser might
catch and discard your whole batch.

For kernel patch, if you know exactly it's D stepping issue, so
just apply the quirk for anything before it, but enable for other
sane HSW, which is the most safe I think.

If let me choose, I'd rather provide a side kernel patch for this
performance issue instead of hack it up in beignet.

-- 
Open Source Technology Center, Intel ltd.

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