[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #35 from Alex Deucher <alexdeucher at gmail.com> ---
(In reply to Chernovsky Oleg from comment #34)
> 
> Is this some kind of open hardware docs? Or just internal? Maybe I missed
> something

Just internal.

(In reply to Chernovsky Oleg from comment #33)
> P.S. I only fear that maybe I launched mmiotrace too late, I did rmmod and
> then modprobe fglrx again. Could it setup any registers at the first run?
> Because at second it touched UVD only when I launched mpv.

To save power the UVD clocks are only raised when it's actually in use.  I
think fglrx does some low level hw init similar to what we do in radeon, but
they don't do a ring test so they probably don't change the UVD plls at driver
load time only when UVD is in use (although I'm not 100% sure off hand).

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