[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #36 from Christian König <deathsimple at vodafone.de> ---
As Alex already noted the detailed register specs are unfortunately only
available internally.

We tried to have at least all the bit definitions needed by the driver
documented in the header files, but some things are just market as for hardware
validation only or debug only etc... and those aren't documented.

(In reply to Chernovsky Oleg from comment #33)
> Yep, I rechecked it and it seems set to 1 always...
> 
> Anyway I gathered around 18 Mb of mmiotrace logs to investigate. Now digging
> through divider and clock registers.

Well it might already help if you provide the values for the UPLL registers
together under fglrx, so that we can compare them to the values Radeon uses.

Regards,
Christian.

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