[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #37 from Chernovsky Oleg <adonai at xaker.ru> ---
Created attachment 113544
  --> https://bugs.freedesktop.org/attachment.cgi?id=113544&action=edit
fglrx mmiotrace dump

(In reply to Christian König from comment #36)
> Well it might already help if you provide the values for the UPLL registers
> together under fglrx, so that we can compare them to the values Radeon uses.
> 
> Regards,
> Christian.

Just thought about that.
Here it is, quite near the place where first related register R/W occured.

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