[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #19 from Alex Deucher <alexdeucher at gmail.com> ---
(In reply to Chernovsky Oleg from comment #18)
> Hm-m, just tried drm-next-3.20 branch and:
> 
> [  365.200918] [drm:radeon_uvd_send_upll_ctlreq [radeon]] *ERROR* Timeout
> setting UVD clocks!
> [  365.200922] [drm:uvd_v1_0_ib_test [radeon]] *ERROR* radeon: failed to
> raise UVD clocks (-110).
> [  365.200928] [drm:radeon_ib_ring_tests [radeon]] *ERROR* radeon: failed
> testing IB on ring 5 (-110).
> 
> 
> Both on cold start and resume from suspend, Pitcairn, Mesa 10.4.3
> Ah yes, the card is factory overclocked (at least box states so)
> 
> It's not very painful for me but if I can help somehow, I'm in

I don't think it will make a difference, but you can try limiting the clocks in
si_apply_state_adjust_rules().  Take a look at the quirk handling code for how
to limit the sclk and mclk.

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