[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=98821

--- Comment #17 from Alex Deucher <alexdeucher at gmail.com> ---
I believe it was this patch that fixed it:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-wip&id=00cfa1ff75340cc11425085fb9f43a6b19a06568

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