[Bug 103922] New:=?UTF-8?Q?=20DP=40Cherryview=20=E2=86=92=20CH7517=20=E2=86=92=20VGA?=: interlaced modes broken

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=103922

            Bug ID: 103922
           Summary: DP at Cherryview → CH7517 → VGA: interlaced modes broken
           Product: DRI
           Version: unspecified
          Hardware: x86-64 (AMD64)
                OS: Linux (All)
            Status: NEW
          Severity: normal
          Priority: medium
         Component: DRM/Intel
          Assignee: intel-gfx-bugs at lists.freedesktop.org
          Reporter: awesome.walrus+bugzilla at gmail.com
        QA Contact: intel-gfx-bugs at lists.freedesktop.org
                CC: intel-gfx-bugs at lists.freedesktop.org

Created attachment 135733
  --> https://bugs.freedesktop.org/attachment.cgi?id=135733&action=edit
DRM driver debug output

Attempted upgrading a video source for a full HD screen system (consumes 720p
and 1080i @50/60Hz via VGA→RGBHV cable, previously served by an nVidia Ion
platform for years).  The new system is built on Celeron N3150, i.e., uses
Cherryview Braswell (Gen8LP) i915 graphics (PCI ID 8086:22b1, rev 0x21).

Problem: interlaced modes do not work, only progressive do.  Specifically, as
found with an oscilloscope, there are no requisite half-lines between odd and
even interlaced fields — vsync start always aligns with hsync start, as opposed
to proper interlaced modes output by the former source, where vsync starts
mid-scanline on every other field, and which work fine.  All other timings seem
OK: e.g., half the scanlines configured are used between vsyncs, vsync duration
is also half-long, etc.

More specifics:
 - OS: Debian 8.8, kernel 4.13.0-0.bpo.1-amd64 (from stretch-backports);
 - the new system has its VGA port appear as “DP2” to the driver; there's also
a CH7517A chip on board (a DisplayPort to VGA translator), which adds up;
 - an example problematic mode (tried many, though):  Modeline "1920x1080 at 50i" 
74.250  1920 2448 2492 2640  1080 1085 1095 1125  Interlace
 - messed with the driver to verify that VSYNCSHIFT gets set to 1128 (for the
mode above) and PIPEACONF gets 0b101 in bits 23:21 (and tried every other way
of requesting interlaced mode via those bits — to no avail);
 - debug logging from the driver setting the aforementioned mode is attached.

Is there any hope?

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