[Bug 103922]=?UTF-8?Q?=20DP=40Cherryview=20=E2=86=92=20CH7517=20=E2=86=92=20VGA?=: interlaced modes broken
bugzilla-daemon at freedesktop.org
bugzilla-daemon at freedesktop.org
Mon Nov 27 17:46:01 UTC 2017
https://bugs.freedesktop.org/show_bug.cgi?id=103922
--- Comment #1 from Ville Syrjala <ville.syrjala at linux.intel.com> ---
Hmm. Indeed looks like DP+interlaced is totally hosed on CHV (and probably VLV
too, perhaps even g4x?). I tested it on an external DP monitor here, and I get
very corrupted output.
I wasn't able to find anything in the docs suggesting that we're doing anything
wrong, nor that we're missing some important register setting. I even found one
chicken bit called 'Flip_MSA_vertical_total_in_interlace_mode' which suggests
that at least someone gave *some* thought to DP+interlaced in the hardware
design.
Frobbing with any of the relevant looking bits didn't help. My display does
correctly identify the mode as 1080i though, so I assume at least some parts of
the MSA packet must be correct.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/intel-gfx-bugs/attachments/20171127/b5cba11a/attachment-0001.html>
More information about the intel-gfx-bugs
mailing list