[Intel-gfx] [PATCH 09/25] drm/915: program driain latency regs on ValleyView
Daniel Vetter
daniel at ffwll.ch
Wed Mar 21 22:00:18 CET 2012
On Wed, Mar 21, 2012 at 12:48:30PM -0700, Jesse Barnes wrote:
> From: Gajanan Bhat <gajanan.bhat at intel.com>
>
> This patch adds support for programming drain latency registers of Pondicherry
> memory arbiter of Valleyview.
s/driain/drain in the subject. I've read drisomething and got momentarily
confused.
>
> Signed-off-by: Gajanan Bhat <gajanan.bhat at intel.com>
> Reviewed-by: Shobhit Kumar <shobhit.kumar at intel.com>
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
> Reviewed-by: Jesse Barnes <jesse.barnes at intel.com>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 +++++++
> drivers/gpu/drm/i915/intel_display.c | 76 ++++++++++++++++++++++++++++++++++
> 2 files changed, 92 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bb6b49f..2ff9822 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2602,6 +2602,22 @@
> #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
> #define DSPFW_HPLL_SR_MASK (0x1ff)
>
> +/* drain latency register values*/
> +#define DRAIN_LATENCY_PRECISION_32 32
> +#define DRAIN_LATENCY_PRECISION_16 16
> +#define VLV_DDL1 0x70050
> +#define DDL_CURSORA_PRECISION_32 (1<<31)
> +#define DDL_CURSORA_PRECISION_16 (0<<31)
> +#define DDL_CURSORA_SHIFT 24
> +#define DDL_PLANEA_PRECISION_32 (1<<7)
> +#define DDL_PLANEA_PRECISION_16 (0<<7)
> +#define VLV_DDL2 0x70054
> +#define DDL_CURSORB_PRECISION_32 (1<<31)
> +#define DDL_CURSORB_PRECISION_16 (0<<31)
> +#define DDL_CURSORB_SHIFT 24
> +#define DDL_PLANEB_PRECISION_32 (1<<7)
> +#define DDL_PLANEB_PRECISION_16 (0<<7)
> +
> /* FIFO watermark sizes etc */
> #define G4X_FIFO_LINE_SIZE 64
> #define I915_FIFO_LINE_SIZE 64
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ea64dc8..efb6465 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4352,6 +4352,80 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> display, cursor);
> }
>
> +static int valleyview_compute_dl(struct drm_device *dev,
> + int plane,
> + int *plane_prec_mult,
> + int *plane_dl,
> + int *cursor_prec_mult,
> + int *cursor_dl)
> +{
Bikeshed, but imo important: Can we make the unimportant part in these
function names less noise and instead make the interesting part readable?
I.e. s/valleyview/vlv/ and s/dl/drain_latency or drain_lat
> + struct drm_crtc *crtc;
> + int clock, pixel_size;
> + int entries;
> +
> + crtc = intel_get_crtc_for_plane(dev, plane);
> + if (crtc->fb == NULL || !crtc->enabled)
> + return false;
> +
> + clock = crtc->mode.clock; /* VESA DOT Clock */
> + pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
> +
> + entries = (clock / 1000) * pixel_size;
> + *plane_prec_mult = (entries > 256) ?
> + DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> + *plane_dl = (64 * *plane_prec_mult * 4) / ((clock / 1000) * pixel_size);
> +
> + entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
> + *cursor_prec_mult = (entries > 256) ?
> + DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
> + *cursor_dl = (64 * *cursor_prec_mult * 4) / ((clock / 1000) * 4);
> +
> + return true;
> +}
> +
> +/*
> + * Update drain latency registers of memory arbiter
> + *
> + * Valleyview SoC has a new memory arbiter and needs drain latency registers
> + * to be programmed. Each plane has a drain latency multiplier and a drain
> + * latency value.
> + */
> +
> +static void valleyview_update_dl(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int planea_prec, planea_dl, planeb_prec, planeb_dl;
> + int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
> + int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
> + either 16 or 32 */
> +
> + /* For plane A, Cursor A */
> + if (valleyview_compute_dl(dev, 0, &plane_prec_mult, &planea_dl,
> + &cursor_prec_mult, &cursora_dl)) {
> + cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> + DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
> + planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> + DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
> +
> + I915_WRITE(VLV_DDL1, cursora_prec |
> + (cursora_dl << DDL_CURSORA_SHIFT) |
> + planea_prec | planea_dl);
> + }
> +
> + /* For plane B, Cursor B */
> + if (valleyview_compute_dl(dev, 1, &plane_prec_mult, &planeb_dl,
> + &cursor_prec_mult, &cursorb_dl)) {
> + cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> + DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
> + planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
> + DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
> +
> + I915_WRITE(VLV_DDL2, cursorb_prec |
> + (cursorb_dl << DDL_CURSORB_SHIFT) |
> + planeb_prec | planeb_dl);
> + }
> +}
> +
> #define single_plane_enabled(mask) is_power_of_2(mask)
>
> static void valleyview_update_wm(struct drm_device *dev)
> @@ -4362,6 +4436,8 @@ static void valleyview_update_wm(struct drm_device *dev)
> int plane_sr, cursor_sr;
> unsigned int enabled = 0;
>
> + valleyview_update_dl(dev);
> +
> if (g4x_compute_wm0(dev, 0,
> &valleyview_wm_info, latency_ns,
> &valleyview_cursor_wm_info, latency_ns,
> --
> 1.7.5.4
>
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--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
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