[Intel-gfx] [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

[Daniel Vetter]

On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote:
> Although internally the MMIO offsets for display regs haven't changed,
> their visibility through the PCI BAR has been affected by the addition
> of the Gunit, which occupies the low part of the address space.
> 
> Display regs on VLV are offset into the BAR by 0x180000, so we need to
> add that for any display register offset.
> 
> This patch is a hack to do just that, but ultimately we need to split
> our display and render code more cleanly and add accessor functions for
> them.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

Gosh, is this horrible ;-) I think a dev_priv->display_mmio_base like
you've proposed + I915_DISPLAY_READ/WRITE like we already have for the
ring stuff is much better ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.c |   83 ++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 81 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a636703..48fc5ab 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1034,6 +1034,80 @@ MODULE_LICENSE("GPL and additional rights");
>          ((reg) != FORCEWAKE)) && \
>         (!IS_VALLEYVIEW((dev_priv)->dev))
>  
> +static bool IS_DISPLAYREG(u32 reg)
> +{
> +	if (reg >= RENDER_RING_BASE &&
> +	    reg < RENDER_RING_BASE + 0xff)
> +		return false;
> +	if (reg >= GEN6_BSD_RING_BASE &&
> +	    reg < GEN6_BSD_RING_BASE + 0xff)
> +		return false;
> +	if (reg >= BLT_RING_BASE &&
> +	    reg < BLT_RING_BASE + 0xff)
> +		return false;
> +
> +	if (reg == PGTBL_ER)
> +		return false;
> +
> +	if (reg >= IPEIR_I965 &&
> +	    reg < HWSTAM)
> +		return false;
> +
> +	if (reg == MI_MODE)
> +		return false;
> +
> +	if (reg == GFX_MODE_GEN7)
> +		return false;
> +
> +	if (reg == RENDER_HWS_PGA_GEN7 ||
> +	    reg == BSD_HWS_PGA_GEN7 ||
> +	    reg == BLT_HWS_PGA_GEN7)
> +		return false;
> +
> +	if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
> +	    reg == GEN6_BSD_RNCID)
> +		return false;
> +
> +	if (reg == GEN6_BLITTER_ECOSKPD)
> +		return false;
> +
> +	if (reg >= 0x4000c &&
> +	    reg <= 0x4002c)
> +		return false;
> +
> +	if (reg >= 0x4f000 &&
> +	    reg <= 0x4f08f)
> +		return false;
> +
> +	if (reg >= 0x4f100 &&
> +	    reg <= 0x4f11f)
> +		return false;
> +
> +	if (reg >= MASTER_IER_VLV &&
> +	    reg <= GEN6_PMIER)
> +		return false;
> +
> +	if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
> +	    reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
> +		return false;
> +
> +	if (reg >= IIR_VLV_RW &&
> +	    reg <= ISR_VLV)
> +		return false;
> +
> +	if (reg == MASTER_IER_VLV)
> +		return false;
> +
> +	if (reg == FORCEWAKE_VLV ||
> +	    reg == FORCEWAKE_ACK_VLV)
> +		return false;
> +
> +	if (reg == GEN6_GDRST)
> +		return false;
> +
> +	return true;
> +}
> +
>  #define __i915_read(x, y) \
>  u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>  	u##x val = 0; \
> @@ -1046,6 +1120,8 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
>  		if (dev_priv->forcewake_count == 0) \
>  			dev_priv->display.force_wake_put(dev_priv); \
>  		spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
> +	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
> +		val = read##y(dev_priv->regs + reg + 0x180000);		\
>  	} else { \
>  		val = read##y(dev_priv->regs + reg); \
>  	} \
> @@ -1065,8 +1141,11 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
>  	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
>  	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
>  		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
> -	} \
> -	write##y(val, dev_priv->regs + reg); \
> +	} else if (IS_DISPLAYREG(reg) && IS_VALLEYVIEW(dev_priv->dev)) { \
> +		write##y(val, dev_priv->regs + reg + 0x180000);		\
> +	} else {							\
> +		write##y(val, dev_priv->regs + reg);			\
> +	}								\
>  	if (unlikely(__fifo_ret)) { \
>  		gen6_gt_check_fifodbg(dev_priv); \
>  	} \
> -- 
> 1.7.5.4
> 
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-- 
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48