[Intel-gfx] [PATCH 19/25] drm/i915: display regs are at 0x180000 on ValleyView

Jesse Barnes jbarnes at virtuousgeek.org
Wed Mar 21 22:36:47 CET 2012

On Wed, 21 Mar 2012 22:33:43 +0100
Daniel Vetter <daniel at ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 12:48:40PM -0700, Jesse Barnes wrote:
> > Although internally the MMIO offsets for display regs haven't changed,
> > their visibility through the PCI BAR has been affected by the addition
> > of the Gunit, which occupies the low part of the address space.
> > 
> > Display regs on VLV are offset into the BAR by 0x180000, so we need to
> > add that for any display register offset.
> > 
> > This patch is a hack to do just that, but ultimately we need to split
> > our display and render code more cleanly and add accessor functions for
> > them.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> Gosh, is this horrible ;-) I think a dev_priv->display_mmio_base like
> you've proposed + I915_DISPLAY_READ/WRITE like we already have for the
> ring stuff is much better ...

I nearly got violent with the hw guys when they told me...

But yeah I think a display reg wrapper with an offset is probably the
least offensive.

Jesse Barnes, Intel Open Source Technology Center
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