[Intel-gfx] [RFC] ValleyView support

Daniel Vetter daniel at ffwll.ch
Wed Mar 21 22:54:27 CET 2012

On Wed, Mar 21, 2012 at 12:48:21PM -0700, Jesse Barnes wrote:
> In this set, you can see why I was asking about register offsets and
> splitting the display code.  Included are a few cleanups to help me keep
> my sanity, but as I mentioned in my other mail I think we should go
> further.
> Many of these are ok to apply as-is, so let me know what order you'd
> like them in and I can re-post and work on the remainder.

Ok, I've gone through this mainly with a view how it integrates with the
current code. I haven't paid too much attention to the vlv enabling code
itself, but given that it's all new hw (that no one really has yet) I'm ok
as long as the new register definitions are properly reviewed. Even if
there are big opens (like the cacheability stuff) I don't mind to much, as
long as it's contained to vlv code paths.

Patch ordering is fine for me, too, safe for the 2 places I complained
about it.

One thing I've missed though is adding pci ids to intel-gtt.c. But while
reading the patches the integration there is rather hackis, so maybe
that's the reason for it. Wrt intel-gtt.c I think we should hold off with
reorganizing this until basic vlv and hsw code has landed. Yeah, that
means adding pci ids at a few more places :(

Cheers, Daniel
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48

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